Semiconductor Industry Larger Masks Are Expected to Pave the Way for High-NA EUV for Large Chips

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High-NA EUV can image finer structures, but so far it has one drawback: the usable exposure field is smaller than that of many EUV systems. ASML plans to work with chip manufacturers to develop larger masks so that, in the future, chips up to about 800 mm² can also be manufactured using high-NA technology.

High-NA EUV is expected to enable semiconductor manufacturing to produce even smaller structures on wafers in the coming years. However, the higher numerical aperture of the new lithography systems comes with a drawback that has received little attention so far: The exposure field is smaller than that of the current generation of EUV systems. This can become a problem for particularly large processors and accelerators.

ASML is therefore working with several major semiconductor manufacturers to find a solution, as the company itself has announced. This means that in the future, larger masks can be used to manufacture dies with an area of up to approximately 800 mm² (1.24  in²)using high-NA EUV. This corresponds roughly to the maximum chip size that current EUV systems can image in a single exposure step. ASML is therefore collaborating with Intel, with Samsung and with TSMC. This was confirmed at the SPIE Photomask Technology + Extreme Ultraviolet Lithography Conference. According to Reuters, interested parties include, among others, Nvidia and SK Hynix, according to Reuters.

High NA Trades Resolution for Image Area

ASML's high-NA systems operate with a numerical aperture of 0.55 instead of 0.33. This allows for the direct exposure of finer structures and eliminates the need for additional multi-exposure steps. ASML reports, for example, that customers are able to replace three EUV masks with one for certain high-NA applications, thereby significantly reducing the number of individual process steps.

However, the anamorphic optics used for this purpose reduce the usable exposure field. For large dies, this has meant until now that they do not fit entirely within the high-NA field. This limitation becomes particularly relevant for large processors and accelerators. The approach of using larger masks is intended to close this gap. According to ASML, the transition could also increase the productivity of high-NA systems by about 40 percent. A pilot application is planned for 2031, and the technology is expected to be ready for volume production starting in 2033.

Larger Chips without Stitching

For the further adoption of high-NA technology, the available exposure area is not merely a question of maximum chip size. In principle, one alternative would be to assemble large structures from multiple exposure fields. However, this type of stitching places greater demands on overlay and process control at the boundaries of the fields.

Larger masks would make it possible to continue exposing large dies as a contiguous structure while simultaneously taking advantage of the higher resolution offered by high-NA lithography. In this way, ASML is addressing a technical limitation that is becoming increasingly significant, particularly as chip areas grow and high-end processors become more complex. The fact that this solution is not expected until the coming decade also shows that optics, masks, resist, metrology, and process integration must be gradually adapted to the new generation of lithography. 

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