Beyond EUV Machinery ASML Aims at Advanced Packaging, Chiplet Stacking, and Bonding

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The boundaries between front-end and back-end production are becoming blurred: In addition to EUV, ASML will focus on packaging, bonding and larger exposure fields in the future, announced CTO Marco Pieters in an interview with Reuters. This is in response to the increased demands placed on chips in the AI age.

With EUV lithography, ASML has a leading technology for the production of advanced chips in small structure sizes. But in the age of AI, it is no longer enough to expose only the finest structures. In an interview with the Reuters news agency, ASML CTO Marco Pieters gave an insight into what kind of tools will be important for the manufacturer of advanced chip manufacturing technologies in the next ten to fifteen years.

From the Front End to Packaging

Advanced packaging is at the heart of this. What was long considered a low-margin back-end process is now becoming a strategic lever for the performance and energy efficiency of modern AI accelerators, says Peters. The growing complexity of chiplet designs is increasingly shifting precision requirements towards packaging and bonding.

Until a few years ago, monolithic dies dominated. Suppliers such as Nvidia and Advanced Micro Devices relied on large, flat chips. Today, heterogeneous systems are created with stacked logic and memory components, connected via the finest through-silicon vias and interposers.

Foundries such as Taiwan Semiconductor Manufacturing Company are driving this development forward with technologies such as CoWoS. Intel is also relying on 3D stacking with Foveros. In both cases, the requirements for overlay accuracy, alignment and process control are increasing significantly.

ASML is therefore examining how existing core competencies from front-end lithography can be transferred to packaging applications. The boundary between front-end and back-end is becoming blurred: optics, wafer handling and high-precision stage systems could also provide competitive advantages in interconnect and bonding processes. The aim is not a broad-based equipment portfolio, but rather targeted expansions with clear technological leverage.

A first step is the XT:260 scanner, which was released at the end of last year and is aimed specifically at advanced memory and AI applications. The system addresses large exposure fields and precise through-silicon alignment and, according to the company, achieves many times the throughput of existing solutions.

Stacking With the Smallest Structure Sizes

The metaphor of a skyscraper aptly describes the current development. AI processors are not only growing in size, but also in height. Several specialized dies are being combined vertically and horizontally to increase bandwidth and computing power.

Memory manufacturers such as SK Hynix are developing suitable HBM generations that are closely interlinked with logic chips. As a result, part of the value chain is shifting from the traditional front end to hybrid process chains, where packaging and lithography are moving closer together.

"Accuracy is becoming increasingly important," emphasizes Pieters. With decreasing tolerances in the sub-micrometer range, it is clear that advanced packaging is no longer just a back-end issue, but increasingly affects front-end standards.

Larger Exposure Fields and High-NA

At the same time, ASML is investigating whether the maximum field size can be extended beyond the current "stamp format". Larger dies could map certain AI workloads more efficiently, but come up against the physical and economic limits of exposure.

At the same time, the next EUV generation is being launched. High-NA systems, which initially went to Intel in 2024, are intended to further increase the structure resolution. A third generation is already in the research phase. EUV therefore remains the core of the business, but is being supplemented by new approaches.

Added to this is the increased use of AI in the company's own systems. Faster machines require more complex control algorithms and inline inspection. Here, software-based optimization can further improve throughput and yield.

For Pieters, one thing is clear: if you want to produce the next generation of AI chips, you have to think of lithography, packaging and system integration as a coherent ecosystem. ASML wants to position itself clearly at this interface in the coming years. (sg)