Chinese Semiconductor Technology Does Huawei Really Exceed the Transistor Density of TSMC's N3E?

Due to a lack of modern lithography equipment, Huawei is moving its computing units into the third dimension. The Kirin 9050 Pro smartphone SoC is expected to outperform top Western chips manufactured using TSMC’s N3E process, but this move comes at a high cost.

The Chinese telecommunications giant Huawei is exploring new ways to circumvent Western technology sanctions. Instead of continuing to shrink transistors across the chip’s surface, the company is stacking circuits on top of each other. In the new Kirin 9050 Pro smartphone processor, the developers have distributed key functional units across two silicon wafers. This so-called Logic Folding is intended to increase transistor density by 55 percent compared to its predecessor and, on paper, even surpass TSMC’s modern 3-nanometer process.

This move also marks the end of a strategic hope. In an essay on the ARXIV platform, Hisilicon CEO He Tingbo makes it clear that China’s semiconductor industry cannot break through the 7-nanometer barrier without modern EUV lithography systems from ASML. Attempts to scale older exposure systems down to 5 nanometers using multiple exposures proved to be a dead end. The Chinese contract manufacturer SMIC hit a wall with its N+3 process: defect rates rose rapidly, and costs skyrocketed.

Shorter Lines Reduce Energy Consumption

By stacking the layers, Huawei is circumventing the lithographic bottleneck. Engineers strategically distribute processor cores, graphics units, and AI accelerators along the longest internal interconnects. This shortens signal paths by 20 to 70 percent and reduces their electrical capacitance. As a result, the circuits consume noticeably less energy: the NPU is expected to be 66 percent more energy-efficient, the GPU 58 percent, and a main CPU core 41 percent. Because signals flow faster, the number of required clock buffers is also cut in half. At the same time, the larger transistor inventory allows for more parallel computation paths, enabling the chip to operate at lower clock frequencies and with lower operating voltages.

Heat Buildup and Buggy Software

The high packing density is not achieved through smaller transistors, but rather by stacking two chips from the older 7-nanometer class on top of each other. For its predecessor, the Kirin 9030, the analysis firm TechInsights found only 120 million transistors per square millimeter. In addition, 50 million contacts spaced 1.5 micrometers (approximately 0.059 mil) apart currently connect the layers, of which only a small fraction actually transmits useful data.

He Tingbo also acknowledges significant hurdles: The company’s in-house design software is still in its infancy because U.S. sanctions block access to proven development tools. In addition, two processing units stacked on top of each other in the cramped smartphone casing generate enormous heat, which can quickly overwhelm the fanless devices. Finally, bonding entire wafers together reduces yield: if just one layer has a defect, the entire assembly ends up as waste.

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