Roadmap for Semiconductor Manufacturing in the AI Era Why TSMC Does Not Rely Solely on Transistor Size

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In modern semiconductor technology, increasing transistor density is no longer sufficient. Memory bandwidth, die-to-die interconnects, and the integration of multiple dies in a package are becoming critical. TSMC therefore combines cutting-edge logic processes with CoWoS, SoIC, and photonics, shifting scaling from the chip to the system level.

Progress in the semiconductor industry has primarily been achieved through smaller transistors for decades. Meanwhile, the bottleneck is increasingly shifting from computational power to data transmission. Billions of calculations per second are of little use if the required data cannot be provided quickly enough from memory. Therefore, HBM and the most energy-efficient connection between memory and computing logic are becoming central factors in system performance.

TSMC bundles this development under its 3DFabric platform. It combines cutting-edge processes with advanced packaging and various levels of integration—from CoWoS (Chip-on-Wafer-on-Substrate) and SoIC (System on Integrated Chips) to optical interconnects.

N2 and A16: More Computing Power per Watt

On the logic side, TSMC is introducing a new transistor generation with N2. For the first time, TSMC is using Gate-All-Around or nanosheet transistors. Compared to FinFETs, they enable higher transistor density and better energy efficiency.

With A16, development takes another step forward. In addition to further scaling of nanosheets, a backside power supply is introduced. Power and signals are thereby more strongly decoupled: power supply is provided via the back of the chip, while the front is available for signal transmission. This reduces contact bottlenecks and improves power density, which is particularly important for high-performance computers and AI accelerators.

But even a more efficient transistor does not solve the memory problem. For that, computational logic must be brought closer to the memory.

CoWoS: HBM Directly Next to the Computational Logic

CoWoS forms the central 2.5D platform for AI accelerators. Logic dies and HBM stacks are placed side by side on a densely wired interposer. This allows for a very high number of parallel connections with short paths for electrical signal transmission.

With increasing computational power, the demand for HBM and the required package area also grows. TSMC is therefore massively scaling CoWoS: For 2026, interposers with 5.5 times the reticle size (exposure field) are planned, and by 2028, a 14-fold version is expected to follow. This should be able to integrate around ten large compute dies and up to 20 HBM stacks.

SoIC: The Third Dimension

CoWoS primarily scales in area. SoIC extends integration vertically. Active dies are stacked on top of each other and connected via high-density die-to-die connections.

With CoWoS and SoIC, a three-dimensional chiplet toolbox is created, where different functions are distributed across various dies and then combined into a system within the package.

For performance, it is not just the number of transistors that matters. The density of interconnects also becomes a scaling parameter. Resistance, capacitance, crosstalk, signal, and power integrity must all be jointly optimized at high data rates.

CPO: The Potential of Optical Interfaces

With increasing package size and a growing number of AI accelerators, electrical data transmission also reaches its limits. Long high-speed connections require powerful interfaces, decoupling, and sometimes retimers, driving up power consumption.

This is where Co-Packaged Optics (CPO) comes into play. Optical transceivers are placed directly next to the high-speed ASIC, drastically reducing the distance for electrical signal transmission.

CPO thus addresses another aspect: CoWoS optimizes the connection between logic and HBM within the package, SoIC the vertical die-to-die integration, and CPO ultimately the energy-efficient communication between packages and systems.

From "More than Moore" to "More System"

TSMC's roadmap thus demonstrates a fundamental shift. The N2 and A16 processes continue to increase computational density and energy efficiency in logic. Additionally, CoWoS connects computing power and HBM. SoIC increases integration density through vertical stacking. Finally, CPO extends scaling to optical communication between system components.

The fact is that the advancement of modern semiconductor technology does not rely solely on how many transistors fit on a die. What matters is how efficiently computing power, memory, and interconnects are combined into a complete system.

The next generation of semiconductors will therefore not only be decided on the wafer but increasingly in the package and in the interconnection technology between the packages.