Billions for Advanced Packaging China Prepares for the Next Chip Shortage

As transistors alone no longer determine the computing power of modern chips, advanced packaging is becoming a strategic bottleneck. China is responding with a new wave of investments: Between May and July 2026, projects worth around 40 billion yuan were announced.

China's advanced packaging industry is experiencing a new wave of capacity expansion. Between May and July 2026, nearly ten major projects were announced, with combined investments of around 40 billion yuan (nearly five billion euros / 5.5 billion USD), reports the technology portal Pandaily.

“Unlike earlier expansion cycles aimed at volume, this wave is focused on the most technically demanding segments of the packaging value chain, driven by the demand for chips for AI and high-performance computing (HPC),” writes the portal.

One reason is that Moore's Law is gradually reaching its limits. “The computing power of an AI chip no longer depends solely on transistor density. It also depends on how many layers of HBM, or high-bandwidth memory, can be stacked on top of each other,” writes the Chinese semiconductor trade publication Bandaoti Qianyan.

This stacking requires advanced packaging technologies such as the CoWoS process (Chip-on-Wafer-on-Substrate) from TSMC, the major Taiwanese contract manufacturer. Packaging now plays a role in determining the performance ceiling of a chip.

Focus on Quality

"The focus has shifted from the question of how to increase the number of transistors per unit area to how to improve the quality of the chip," the South China Morning Post quoted Zheng Li, the head of the packaging and testing company Jiangsu Changjiang Electronics Technology (JCET), as saying. He spoke at the industry conference Semicon China.

Three major projects stand out. On June 24, JCET announced the construction of a new packaging and testing factory in the Lingang Special Area in Shanghai. 7.8 billion yuan (around 950 million euros / approx. 1.08 billion USD) will be invested there in new production lines for high-density redistribution layers (RDL), ultra-fine bumping, large-format heterogeneous integration, and chiplet packaging.

There is especially demand for this in the market for AI servers, HPC systems, and graphics processors. The first phase of this project is set to become operational in the second half of 2028. "The new capacities will primarily be built around demand from the AI industry, with a particular focus on advanced packaging requirements for computing power, data storage, and power supply," writes the Chinese financial journal Zhengquan Shibao.

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JCET has increased its investment budget for 2026 to around 10 billion yuan (approximately 1.2 billion euros / approx. 1.38 billion USD ), an increase of almost 18 percent compared to the previous year. According to the company, capacity utilization in the first quarter was over 80 percent. The order books are apparently full.

Further Major Investments

Two days after JCET, Forehope Electronic announced plans to invest 10.3 billion yuan (around 1.3 billion euros / approx. 1.42 billion USD) over eight years in a packaging and testing facility in Yuyao near Ningbo. Four production lines for bumping, 2.5D integration, flip-chip, and advanced wire bonding are to be established there. Target markets include AI edge processors, automotive control chips, and high-quality analog ICs.

The third major project started on July 13 in Jiading, a district of Shanghai. A subsidiary of Union Semiconductor from Hefei is investing at least 7.5 billion yuan (more than 900 million / euros approx. 1.04 billion USD) there in the "HITS" packaging process, ultra-fine bonding, high-density RDL, and large-scale heterogeneous integration, again for AI servers and HPC systems.

Part of the new packaging wave is driven by chip demand in the automotive industry. In mid-July, HKC signed a contract for a packaging and testing base worth four billion yuan (around 500 million euros / approx. 550 million USD) in Shaoxing, Zhejiang Province. After the first expansion phase, 20 million packaged chips in a 12-inch equivalent are expected to roll off the production line monthly, primarily automotive-grade components and power analog ICs.

Boom, also Thanks to the Automotive Industry

The new factories are usually being built right next to existing wafer plants or large automotive sites to strengthen local semiconductor supply chains, writes Pandaily. In Shaoxing, for example, UNT is already producing wafers for the automotive industry on a large scale.

A second focus is memory chips. The AI industry is struggling with the "memory wall," a new bottleneck between processor and memory. According to reports in Chinese trade media, the packaging of memory modules is therefore shifting to fan-out architectures and the integrated packaging of memory and computing chips.

Huatian Technology is currently expanding its base in Nanjing for three billion yuan (around 370 million euros / approx. 415 million USD), including packaging for HBM and testing for SSD controllers, reports Pandaily. Biwin Storage has also launched a project worth one billion yuan (around 120 million euros / approx. 138 million USD) in the southern Chinese Greater Bay Area for packaging AI memory chips. Partly, these investments are driven by the technology boycotts imposed by Washington against Beijing.

"TSMC's CoWoS capacity is stretched to its limits, the American CHIPS Act is injecting funds into domestic packaging, and Apple had to significantly raise the prices of MacBooks and iPads," writes Bandaoti Qianyan. It is evident that advanced packaging is replacing wafer manufacturing as the scarcest link in the semiconductor supply chain.

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Packaging in Taiwan at Full Capacity

The packaging capacities of TSMC in Taiwan are now more than fully utilized, according to reports. TSMC's CoWoS utilization has been above 120 percent for some time. The share of packaging in the manufacturing costs of top-tier AI chips has risen from less than ten percent to more than 25 percent.

Investors like such "bottlenecks." While Washington's export controls deny Chinese manufacturers access to contract manufacturers like TSMC, advanced packaging in China is becoming increasingly lucrative.

The reason is technical but simple. The harder it becomes to access the finest chip feature sizes, the more important it becomes to extract more computing power from existing dies through stacking and interconnection.

Thus, advanced packaging has become part of the "chip war" between the USA and China. "The strategic goal of the United States is clear. They not only want to bring wafer manufacturing back to American soil but also rebuild a complete domestic ecosystem for advanced packaging, a segment that until recently was almost entirely dependent on Asia," writes Bandaoti Qianyan.

Intel has received $8.5 billion in direct subsidies, partly for packaging projects. TSMC is getting $6.6 billion for expansion in Arizona. Samsung has received $6.4 billion for Texas, and the packaging specialist Amkor around $407 million for a complete packaging and testing factory, also in Arizona.

The development in China mirrors these efforts in the USA. JCET, Huatian, and Tongfu Microelectronics are currently entering a "rare strategic time window," writes Bandaoti Qianyan. In China, they benefit from the fact that Chinese chip customers prefer domestic service providers for political reasons. Additional demand comes from abroad, as leading international foundries are currently focusing their resources on 3D packaging. JCET specifically aims to capture the overflowing 2.5D orders, writes Zhengquan Shibao. Rarely has geopolitics so directly contributed to a boom in an industry in China as it is currently doing for chip packaging providers.