DARE SGA1 Europe Builds Its Own Infrastructure for Supercomputing

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AI for drug discovery, high-performance computing for climate models, software development for autonomous vehicles—ever more complex tasks are reinforcing the need for powerful hardware and software infrastructure. A cross-border initiative with partners from across Europe, including the Technical University of Munich, is working on its own high-performance chips and software for supercomputers.

Europe is taking its digital future into its own hands and launched "Digital Autonomy with RISC-V in Europe", or DARE SGA1 for short, in March 2025, a project that reduces dependence on non-European hardware and software solutions. 38 partners from 14 countries are jointly developing critical components such as semiconductors, processors and software to create advanced computing and AI systems for research and industry. The project aims to help secure Europe's economic stability and technological competitiveness.

TUM Campus Heilbronn Develops Parallel Debugger

As part of the DARE SGA1 project, TUM is developing a parallel debugger that recognizes errors in source code and thus simplifies software development. Since a large part of development time today is spent on understanding, finding and correcting software errors, debuggers are a key factor for productivity in software development.

Our team, which also includes Professor Martin Schulz, doctoral student Kun Qin and student Nima Baradaran Hassanzadeh, has developed a tool that makes the contents of special computing memories visible and shows how they change during program execution.

With the help of feedback from developers, the debugger should find errors in parallel systems even more efficiently. Parallel systems are applications that run simultaneously on several processors or computing units. For a debugger to become a parallel debugger, three levels must be covered:

• Data parallelism: simultaneous calculations of several elements of a vector or matrix with one command
• Thread parallelism: computing units working in parallel with shared memory
• Parallelism with distributed memory: Many individual computers communicate with each other via messages.

The software solutions are to be published under open source licenses so that external players can use the results, develop them further and adapt them to their own requirements.

Open Processor Architecture RISC-V as the Hardware Foundation

In the DARE project, the open standard not only shapes software development. The RISC-V processor architecture also deliberately follows the open source concept so that DARE SGA1 can receive broad support through growing participation. RISC-V still plays a minor role in high-performance computing, but the collaborative approach should soon fundamentally change this.

The DARE project relies on chiplets designed in Europe with the latest silicon technology. The hardware is designed to combine maximum performance with energy efficiency. Three RISC-V-based chiplets are at the heart of the hardware development:

• Vector accelerator (VEC) for high-precision high-performance computing (HPC) and applications in the field of HPC/KI convergence, developed by Openchip
• AI Processing Unit (AIPU) for accelerating AI inference in HPC applications, developed by Axelera AI
• General-purpose processor (GPP), optimized for HPC workloads in European supercomputers, developed by Codasip

These chiplets are developed in CMOS technology nodes and brought to tape-out, i.e. worked up to the finished chip design and handed over to production. Thanks to their architecture, the chips are more efficient, more scalable and cheaper, thus overcoming the limitations of traditional monolithic chips. In addition to HPC and AI applications, RISC-V research is targeting other fields such as automotive, aerospace, personalized medicine, climate modelling and bioinformatics applications.

Exascale Supercomputer as a Declared Goal

The RISC-V processor architecture is intended to produce supercomputers that operate in the exascale and post-exascale range. Exascale refers to a computing power of one exaflop - one trillion (10^18) FLOPS (floating point operations) per second. The term shows the ambition of the project: it is about the highest performance class of supercomputers worldwide. The first exascale supercomputer went into operation in the USA in May 2022 and is called "Frontier". It replaced the fastest supercomputer to date, "Fugaku" from Japan, which topped the list in 2020 and was based on ARM architecture. Post-exascale means that the DARE project already has its sights set on the next generation, which will exceed the speed of today's supercomputers.

Hardware-Software Co-Design as a Development Strategy

DARE SGA1 follows a consistent co-design approach and uses a carefully selected set of European HPC and AI applications for development control. In parallel to the hardware development, a complete software stack is created that is tailored to the DARE chips. Early access to RISC-V emulation and simulation allows developers to test the software before the finished chips are available.

The Barcelona Supercomputing Center is coordinating the six-year project. The first three-year phase has a budget of 240 million euros (approx. USD 283 million) and aims to lay the foundations for Europe's first fully independent HPC system by 2028. The long-term goal: a complete European supercomputing value chain - from chip development and software to applications in science, industry and AI. (sg)