Microelectronics for Autonomous Systems Chip Maps 3D Environments in Real Time with Only Six Milliwatts

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Researchers at MIT have developed an SoC that allows tiny robots to capture their surroundings in three dimensions with extremely low power consumption. A tight integration of hardware and algorithm reduces the energy requirement to an absolute minimum.

Small autonomous robots and battery-powered devices face a significant challenge when navigating complex environments. Creating detailed 3D maps typically requires substantial computing power and large storage to spatially map obstacles. Drones, for example, that inspect industrial ventilation systems for gas leaks, or lightweight augmented reality headsets, often lack the necessary battery capacity for these conventional methods.

Researchers at the Massachusetts Institute of Technology are addressing this bottleneck with a new system-on-a-chip called Gleanmer. This hardware enables autonomous systems to map their surroundings in real time while consuming only about six milliwatts of electrical power – roughly the equivalent of a single LED's energy requirement. A robot can directly use this map to plan a collision-free path to its destination.

Departure from Memory-Intensive Voxels

Conventional methods for spatial mapping rely on three-dimensional pixels, known as voxels. This approach demands substantial memory since each depth capture must be loaded and processed multiple times. The research team at the Massachusetts Institute of Technology, however, employs a technique that represents space using ellipsoidal shapes, referred to as Gaussian functions. The size, shape, and thickness of these ellipsoids can be flexibly adjusted, allowing them to conform much more effectively to curved objects compared to rigid voxels. A single elongated ellipsoid can cover an area that would otherwise require many voxels, enabling the chip to capture obstacles and free spaces much more compactly.

The high efficiency of the chip results from the co-design of hardware and software. The researchers specifically designed the chip to accelerate a custom-developed algorithm called GMMap. Instead of comparing every pixel in a 3D image with all others, the algorithm assumes that neighboring pixels belong to the same Gaussian function. Therefore, it only compares image points with their direct neighbors. In this way, the chip generates highly precise representations from depth images in a single pass. The system then immediately discards the images, meaning the chip never has to hold an entire image in memory.

Local Storage and Direct Data Fusion

"At any given time, we only need to store a few pixels in memory, which significantly reduces the memory requirements of our algorithm," explains Peter Zhi Xuan Li, a doctoral student and co-lead author of the study. As a robot moves through space, overlapping Gaussian functions inevitably occur due to different angles of view, since they represent the same object. The algorithm merges these directly without needing to revisit the original image pixels.

The researchers use this principle to design the chip so that it keeps the active Gaussian functions in small, fast memory units located directly next to the processing cores. This eliminates the need to retrieve data from more distant, energy-intensive external memories outside the chip. Zih-Sing Fu, also a doctoral student at the institute, clarifies: "By using a dedicated memory that only holds the objects from the last few frames, data can be accessed much more efficiently."

Enormous Savings Potential for Edge Devices

The developers tested the system-on-a-chip by reconstructing various real 3D environments. The component also successfully processed live data directly from a smartphone camera. With an energy consumption of just six milliwatts, Gleanmer requires only about 2.5 percent of the power that the previous best chip for mapping would need. Since the chip reuses compact data for path planning, the robot records its route using only about 20 percent of the typically required energy. Li summarizes: "We reduce the memory demand by ensuring the algorithm is efficient. Then we accelerate the workload executed by this efficient algorithm so that our chip is ultimately as efficient as possible."

The team recently presented the work at the IEEE Very Large-Scale Integrated Circuits Symposium. In the future, the researchers plan to place the computing units on the chip even closer to the sensors to save more energy, as well as to evaluate the use of the technology for reading schematics.