Semiconductor Development Cadence And Samsung Foundry Expand 2nm And 3D IC Cooperation

From Sebastian Gerstl 2 min Reading Time

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Cadence and Samsung Foundry are expanding their collaboration for 2nm and 3D IC designs. The goal is a signoff-capable platform for AI, HPC and edge chips.

Cadence and Samsung Foundry have developed a portfolio of memory and interface IP and expanded the certification of Cadence design and analysis flows for agentic AI, digital circuits, custom circuits, 3D ICs and system design (SDA) for Samsung Foundry's second-generation 2nm process.(Image: Samsung Foundry)
Cadence and Samsung Foundry have developed a portfolio of memory and interface IP and expanded the certification of Cadence design and analysis flows for agentic AI, digital circuits, custom circuits, 3D ICs and system design (SDA) for Samsung Foundry's second-generation 2nm process.
(Image: Samsung Foundry)

Cadence and Samsung Foundry have announced a multi-year expansion of their collaboration. The focus is on an expanded portfolio for memory and interface IP as well as certified design flows for Samsung's second-generation 2nm process technology. The platform is intended to support developers of AI infrastructure, HPC systems, edge AI chips and physical AI applications.

The agreement follows on from the certification of Cadence tools and IP for several Samsung Foundry nodes announced in 2025. New is the broader coverage of high-speed SerDes, PCIe, UCIe, leading memory interfaces and NVIDIA NVLink C2C-capable interconnects. CUDA-X GPU-accelerated libraries are also part of the expanded range.

Certified Flows for 2 nm Designs

Cadence provides a comprehensive, certified flow for Samsung's second 2nm generation. This includes Innovus for digital implementation, Virtuoso Studio for analog and custom designs, the Integrity 3D-IC Platform for system design and implementation, and Voltus for power integration and system power analysis. Quantus and Tempus complete the flow for extraction and timing signoff.

The flow is enhanced by glitch power optimization in Genus and Innovus as well as a smart hierarchical approach for place-and-route. This is intended to help developers achieve better results in terms of performance, power and area for large AI and HPC designs, while at the same time shortening the lead time to tapeout.

Samsung's 3D Cube H technology is also included in the collaboration. For Hybrid Copper Bonding, the flow includes system planning, implementation, analysis, verification and signoff. Among others, Cadence Cerebrus, Integrity 3D-IC, Innovus, Voltus and Pegasus are involved. Automated routing and optimization for silicon interposers are also included.

Cadence and Samsung Foundry plan to showcase the expanded collaboration at the Samsung Advanced Foundry Ecosystem Event SAFE 2026. Technical sessions and demonstrations on 2nm and 3D IC flows for GPU-accelerated AI workloads are planned. For chip developers, the announcement is particularly relevant because it promises a more integrated environment of foundry process, IP, EDA tools and signoff for complex AI designs. (sg)

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