Chip Design Huawei Aims to Achieve 1.4 nm Equivalent By 2031

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With the Tau Scaling Law and the LogicFolding architecture, Huawei presents an alternative approach to increasing chip performance without relying exclusively on smaller transistors. The aim is to achieve a transistor density equivalent to a 1.4 nm process by 2031.

At the IEEE International Symposium on Circuits and Systems (ISCAS) 2026 in Shanghai at the end of May, Huawei presented a new basic principle for the further development of semiconductors. This is a principle called the Tau Scaling Law. He Tingbo, President of Huawei's Semiconductor Business Unit, explained the concept in her ISCAS keynote "New Semiconductor Path in Practice". It is the first time that a semiconductor principle originating from China has been proposed as a possible industry framework, comments TrendForce.

The starting point is an observation that concerns the entire semiconductor industry: Moore's Law, the decades-old guideline according to which the transistor density on a chip doubles every two years, is increasingly reaching its physical and economic limits. The further miniaturization of transistors is becoming increasingly difficult and expensive—and only makes limited economic sense. According to Huawei, it has been working on an alternative scaling principle for the past six years, which is not based on geometric miniaturization, but on the reduction of signal propagation times.

Tau Instead of Nanometers: The Basic Principle

Put simply, the Tau Scaling Law replaces geometric scaling with time-based scaling. The decisive parameter is no longer the transistor size, but the time constant τ—i.e. the time that signals and data need to move through chips and computer systems. Systematically reducing this value increases performance and energy efficiency without necessarily having to rely on smaller production nodes. This is how the engineers at Huawei see it. And the basic physical idea behind it is correct—less RC delay means higher performance and better energy efficiency. In this way, Huawei wants to benefit more from advances beyond pure process miniaturization.

Huawei has developed a multi-level co-optimization framework comprising four levels to support the developed thesis. At the device level, the resistance and parasitic capacitance of transistors and connecting lines are minimized in order to reduce the physical time constant at the base. At circuit level, the LogicFolding architecture is used: it dissolves the physical limits of traditional circuit layouts, shortens critical signal paths and thus reduces resistive and capacitive loads. This is achieved by the three-dimensional arrangement of the logic circuits, which were previously laid flat on one level. This reduces signal paths and runtimes without the transistors themselves having to become smaller.

At chip level, a fully coordinated design of software, architecture and silicon ensures fine-grained control of instruction and data flows. And at system level, the UnifiedBus protocol redefines interconnects for computing systems and enables unified memory addressing for SuperPoDs—with the aim of significantly reducing communication latencies at system level.

LogicFolding in Practice

The first full implementation of the new architecture will be in the Kirin chipset, which Huawei has announced for fall 2026. According to He Tingbo, LogicFolding delivers 55 percent higher transistor density and 41 percent improved energy efficiency compared to traditional designs, "not through a new lithography step, but through a topological reorganization of the spatial distribution of logic in three dimensions," as she explained at the conference. Huawei also claims to have applied the Tau Scaling Law to varying degrees in 381 chip designs for smartphones, networking and AI computing over the past six years.

Claim And Open Questions

By 2031, Huawei wants to use this approach to develop chips with a transistor density corresponding to the 1.4 nm level, i.e. the level that TSMC and Intel are targeting for 2028 and 2029 respectively. Huawei has not yet presented any independent performance data. It remains to be seen whether the key figures presented can be reproduced under real conditions.

The geopolitical background cannot be separated from the technical demands: US export controls have largely cut off Huawei's access to leading lithography tools and other key technologies. The Tau Scaling Law is therefore also an answer to the question of how chip performance can be increased if the conventional route via ever smaller production nodes is blocked.

Nvidia CEO Jensen Huang recently admitted that they had lost the Chinese market for AI chips. AMD CEO Lisa Su also does not expect any significant sales in China for her high-end AI chips. If Huawei's new design approach proves successful in practice, this could further strengthen the technological independence of the Chinese semiconductor ecosystem. (sb)

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