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Integration Process Industrial-Scale 12 Inches Process for 2D Transistors

By Sebastian Gerstl | Translated by AI 2 min Reading Time

Imec, ASML, and TSMC have unveiled a 12 inches process for transistors made from 2D materials. It is designed to scale n- and p-FETs with a 50-nm CPP to wafer sizes relevant to industrial production.

Figure 1: (A) X-Cut HAADF scanning electron microscopy image of a WS2 device with a CPP of 50 nm, a contact length of 19 nm, and a width of 256 nm after etching the gate interconnect. (B) The corresponding energy-dispersive X-ray spectroscopy (EDS) analysis(Image: Imec)
Figure 1: (A) X-Cut HAADF scanning electron microscopy image of a WS2 device with a CPP of 50 nm, a contact length of 19 nm, and a width of 256 nm after etching the gate interconnect. (B) The corresponding energy-dispersive X-ray spectroscopy (EDS) analysis
(Image: Imec)

Imec, ASML, and TSMC have developed a new integration process for transistors based on two-dimensional materials. The focus is on n-FETs and p-FETs on 300-mm wafers. According to the partners, scaled devices of both polarities with a contacted poly pitch (CPP) of 50 nm have been demonstrated for the first time.

The n-FETs use MoS₂ as the channel material. WS₂ or WSe₂ were used for the p-FETs. The devices were fabricated using EUV lithography.

2D Materials for Future Logic Devices

Transition metal dichalcogenides such as MoS₂, WS₂, and WSe₂ are considered potential channel materials for highly scaled transistors. They are atomically thin and can complement or replace silicon in certain device designs. The technical advantage lies primarily in the electrostatic control of the channel at very short gate and channel lengths. At the same time, the materials are expected to enable sufficiently high charge carrier mobility. According to Imec, the process now presented is compatible with back-end applications and is intended to be suitable for both highly scaled logic as well as back-end-of-line and wafer-backside applications.

The results include n- and p-FETs with a 50-nm CPP, a very low off-current at a gate voltage of 0 V, and p-FETs with a WSe₂ channel, whose performance is on par with top-quality laboratory devices.

According to the partners, 94 percent of the transistors were functional. The criterion used was an Imax-to-Imin ratio of more than 10⁵. The n- and p-FETs were integrated on the same 12 inches wafer.

The process is not intended to be limited to the three materials mentioned. Imec, ASML, and TSMC believe that the process can also be applied to other 2D channel materials.

Thin-Film Transistors And Single-Patterning EUV Lithography

Figure 2: MoS₂ n-FETs and WSe₂ p-FETs with a contact spacing of 50 nm and a relaxed channel width (650 nm), integrated on the same 12 inches wafer, exhibit good threshold voltage matching.(Image: Imec)
Figure 2: MoS₂ n-FETs and WSe₂ p-FETs with a contact spacing of 50 nm and a relaxed channel width (650 nm), integrated on the same 12 inches wafer, exhibit good threshold voltage matching.
(Image: Imec)

A key feature is the so-called inverted thin-film transistor process. Unlike in conventional 2D transistors, the contacts are located at the bottom, while the gate is deposited on top of them.

To achieve this, the TMD channel material is deposited onto pre-structured trenches filled with tungsten, which serve as contacts. This structure is designed to ensure that both transistor polarities turn off at a gate voltage of 0 V.

According to the partners, single-patterning EUV lithography played a key role in scaling. This enabled the production of transistors with channel lengths as small as 28 nm and a pitch suitable for advanced transistor nodes.

TSMC views this work as a step toward reducing technical risks during the transition from the lab to production. ASML points to the higher resolution of EUV lithography, which enables smaller structures than previous lithography processes. (sg)

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