3D Chip Integration Imec and Sony Develop a New Isolation Process for Backside Contacts

Related Vendors

FAULHABER Drive Systems

SIMTOS (Seoul International Machine Tool Show)

A novel approach to 3D semiconductor integration optimizes the connection of the chip's backside. The localized isolation process significantly reduces the resistance of through-silicon vias and simplifies complex manufacturing.

At the IEEE/JSAP Symposium on VLSI Technology and Circuits in June 2026, the research center Imec and Sony Semiconductor Solutions Corporation presented a jointly developed integration module. The technology aims to integrate so-called front-to-back through-silicon vias (TSVs) more densely and efficiently into semiconductors. These backside connections are considered a key component for 3D stacking, where multiple chip layers are stacked on top of each other. The developers are addressing the ever-growing challenge of reliably interconnecting the extremely fine structures on the active wafer front side with the much coarser structures on the wafer backside.

Until now, the industry has often relied on the via-middle TSV method for these connections. However, this approach presents physical challenges: the resulting vias typically exhibit an unfavorable aspect ratio, making subsequent metallization in production more difficult and hindering the electrical performance of the chips. Sony and Imec, on the other hand, are using a self-aligned localized dielectric isolation on the backside, referred to by the institutes as Local-BDI. This isolation structure specifically forms at the point where the vertical connections and the active area of the front side overlap.

Gallery

Lower Resistance and More Tolerance in Manufacturing

With this modified structure, the vias on the bottom and top sides are 50 percent larger than with conventional approaches. This not only simplifies the introduction of the metal but also reduces electrical resistance to one-third. Zsolt Tokei, Program Director for 3D System Integration at Imec, explains the technical leap: “Building on the already existing high-density and narrow vias on the front side of the wafer (i.e., the middle-of-line vias (MOL)), our module enables for the first time the transition to significantly wider TSV connections between the active front side and the back side of the wafer.”

At the same time, the Local-BDI process allows for much greater variability in mass production. The tolerance for misalignments between the vertical channels and the tiny contacts of the middle interconnect layer increases to up to 30 nm. The researchers demonstrated this using a standard cell configuration with a height of 115 nm. Measurements of leakage currents also showed that the structures effectively isolate the surrounding silicon substrate within this enlarged tolerance window.

Wafer-to-Wafer Hybrid Bonding

Imec And EVG Demonstrate High-Precision Hybrid Bonding With 200 nm Pitch

Module is Suitable for Thick Silicon Layers

The manufacturing process integrates into existing industry standards. It begins with the conventional processing of the lower, middle, and upper interconnect levels (FEOL, MOL, BEOL), before the wafers are physically bonded and the silicon is thinned. Only then do the machines deposit a conformal dielectric, etch the material isotropically, and fill the newly created channels with metal.

This method opens up entirely new design possibilities, particularly for certain memory modules. Unlike alternative concepts, manufacturers do not need to completely remove the remaining silicon. "The Local-BDI module will enable new 3D integration concepts for a variety of use cases—including advanced logic and memory applications," Tokei further explains. "Moreover, our module, unlike backside integration concepts that rely on the removal of the remaining bulk silicon, allows the connection of TSVs through bulk silicon with a thickness of up to 500 nm. This is of interest for applications such as DRAM that utilize the relatively thick silicon layer remaining on the wafer’s backside."

Takushi Shigetoshi, Senior Manager at Sony and lead author of the study, contextualizes the development within the broader market: "3D integration is becoming increasingly important in a variety of semiconductor applications, and it is crucial to develop different concepts for backside connectivity that can be selected based on the target application." 

Semiconductor Manufacturing

Precision Measurement in Real Time to Improve Yield And Process Stability