Imec And EVG Demonstrate High-Precision Hybrid Bonding With 200 nm Pitch

Wafer-to-Wafer Hybrid Bonding Imec And EVG Demonstrate High-Precision Hybrid Bonding With 200 nm Pitch

2026-06-01 From Sebastian Gerstl | Translated by AI 2 min Reading Time

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Imec and EV Group have presented a wafer-to-wafer hybrid bonding technology with a pad pitch of 200 nm for copper interconnects at the IEEE Electronic Components and Technology Conference 2026. The technology is aimed at future 3D stacks of logic and memory layers.

Figure 1: Example of a possible division of an SoC according to Imec's CMOS 2.0 scaling paradigm. The Belgian research institute and Imec, together with the EV Group, have demonstrated wafer-to-wafer hybrid bonding with 200 nm pad spacing.(Image: Imec) — Figure 1: Example of a possible division of an SoC according to Imec's CMOS 2.0 scaling paradigm. The Belgian research institute and Imec, together with the EV Group, have demonstrated wafer-to-wafer hybrid bonding with 200 nm pad spacing.
(Image: Imec)

The process was demonstrated on a test carrier with routable connections. The development is aimed at future 3D-integrated semiconductor architectures. The focus is primarily on stacks of logic-to-logic and memory-to-logic levels, which require significantly higher connection densities than current assembly and connection technologies.

Imec's CMOS 2.0 concept envisages splitting a system-on-chip into several functional levels and bringing them together again using 3D interconnect technologies. A very small interconnect pitch is a key requirement for such architectures.

Gallery

Figure 3: Improvement of the actual alignment achieved in wafer-to-wafer bonding on wafers with electrical components. The results are shown with and without the application of corrections using hybrid pad lithography before bonding.(Image: Imec/IEEE)

Figure 2: TEM image of daisy-chain structures on a hexagonal 200 nm pad grid with a uniform hybrid pad size and a target Cu density of 25 %.(Image: imec/IEEE)

Figure 4: Cumulative representation of the measured resistance per joint for structures with the same pad size and a copper density of 25 %.(Image: Imec/IEEE)

According to Zsolt Tokei, Imec Fellow and Program Director for 3D System Integration, the fine-pitch hybrid bonding result was achieved by jointly optimizing all critical elements of Imec's hybrid bonding process flow. "These include the use of SiCN as the dielectric material and a chemical mechanical polishing (CMP) step prior to bonding," says Tokei. "The latter was optimized for high uniformity across the entire wafer to create extremely flat dielectric surfaces while achieving a controlled indentation of a few nanometers for the Cu pads. The high overlay accuracy and control enabled by EVG's wafer bonding tool was further supported by an improved Cu pad design and by lithographic corrections prior to bonding."

Process Optimization for Fine Interconnects

In the study shown, four layers of routable interconnects were prepared on each of the two 300 mm wafers before bonding. After bonding, the Cu pads achieved a pad-to-pad overlay vector of less than 40 nm across all chips of the wafer, according to Imec. EVG's GEMINI FB wafer bonding system was used for hybrid and fusion bonding. According to the partners, overlay control was a key factor in supporting electrical yield at fine pad pitches.

Imec and EVG want to further develop the roadmap for wafer-to-wafer hybrid bonding towards interconnect pitches below 200 nm. This requires additional improvements in overlay accuracy, surface planarity and process stability. (sg)

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