Chip Design under US Sanctions Huawei Folds Chips; Huang Slows Down the Enthusiasm

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With LogicFolding and the Tau scaling law, Huawei aims to increase the performance of future chips through shorter signal paths and more efficient architectures. In China, the approach is being celebrated as a breakthrough. Nvidia CEO Jensen Huang sees it as progress for Huawei, but not yet a threat to TSMC's leading manufacturing processes.

The Chinese technology company Huawei has introduced a new design principle for chips that aims to enhance their performance through faster signal and data flow. With this alternative to the continued miniaturization dictated by Moore's Law, Huawei seeks to bypass US boycotts and build its own high-end chips by 2031, achieving a transistor density equivalent to 1.4-nanometer processes.

This new "Tau (τ) scaling law," as we reported, was recently presented by He Tingbo, the head of Huawei's semiconductor division. "Losing geometric scaling does not mean losing temporal scaling," the business portal 36Kr quoted the Huawei manager.

Chip Design

Huawei Aims to Achieve 1.4 nm Equivalent By 2031

Concentrating more and more transistors in increasingly smaller spaces has become technically more challenging and costly in recent years. For Huawei, the search for alternative performance boosters became even more urgent after the company was placed on the notorious "Entity List" by the US government in 2019, restricting its access to advanced semiconductor technology from the USA.

Because the USA has also put massive diplomatic pressure on the Netherlands and Japan to support their "technology war" against China, the import of EUV lithography machines from the Dutch monopoly manufacturer ASML into the People's Republic has become difficult to nearly impossible.

Without it, chips smaller than around seven nanometers cannot currently be produced economically at truly large scales. Despite all efforts, China has not progressed much further with miniaturization, while TSMC in Taiwan is already producing 2-nanometer processes and plans to begin 1.4-nanometer process manufacturing by 2028. It is only against this backdrop that Huawei's announcement of its 1.4-nanometer goal by 2031 becomes understandable.

Similarity Instead of Copy

Huawei is therefore not attempting to achieve 1.4 nm itself but instead aims to make less densely packed transistors on semiconductors equally powerful. The electrical resistance is reduced so that signals take less time to traverse the circuits. This is where the term "Tau Scaling" used by Huawei comes from, named after the Greek letter τ (tau), which represents the time constant in electrical engineering and signal propagation time in chip manufacturing.

This reduces the signal propagation time across all levels, from the individual transistor to the circuit and up to the entire system, i.e., across the entire computing stack. This way, computational performance and energy efficiency can be increased without reducing the size of the transistors themselves.

Specifically, Huawei uses a new chip design called "LogicFolding" for this. The logic circuits of a chip are no longer arranged flat side by side but are folded and stacked in two layers on top of each other.

"Before LogicFolding, it took three years to increase the transistor density from 126 to 155 million transistors per square millimeter," He said during the presentation of the new architecture. "In 2026, LogicFolding will boost it in a single step to 238 million transistors per square millimeter."

Huawei cites a 55 percent higher transistor density and a 41 percent better energy efficiency for the new design.

Technology for Smartphones

The company announced that the next generation of Kirin smartphone chips will be the first to use LogicFolding. These are expected to hit the market in the fall. Later, by 2030, the Ascend chips, which are central to China's hopes for improved AI data centers, will also be optimized with this technology. Large AI clusters consisting of hundreds or thousands of chips are also set to be accelerated by it.

"What Huawei is proposing is a shift from traditional node-driven scaling to efficiency scaling at the system level," said He Hui, Director of Semiconductor Research at market research firm Omdia. Instead of relying solely on ever-smaller transistors, Huawei is focusing on shortening connections, reducing latency, and improving data flow within the chip.

Driven by a clever PR strategy from Huawei and the widespread desire in China to stand up to the Americans and the Trump administration, Chinese media were full of exuberant praise for Huawei's new architecture.

"Huawei overthrows Moore's Law," headlined the technology portal Huxiu. For the first time, a Chinese manufacturer has proposed a new guiding principle for the global semiconductor industry, wrote the People's Daily (Renmin Ribao). Everywhere there was talk of a "breakthrough in semiconductor manufacturing," just like in Huawei's press releases.

Experts Slow Down

It took a sharp mind and proven experts like Jensen Huang to deflate this overhyped Tau balloon a bit. "This is certainly a breakthrough for Huawei," said the Nvidia CEO. However, it is not necessarily a threat to the world market leader TSMC, Huang added. Moore's Law also remains relevant. What Huawei is doing is impressive, according to the Nvidia CEO, but not entirely new. Taiwan has been working on similar optimization approaches such as die-stacking, 3D packaging, and hybrid bonding for many years.

Other analysts curbed the Chinese enthusiasm by pointing to unresolved technical hurdles for "LogicFolding." Folding and stacking circuits, among other things, increases the complexity of architectures and makes heat dissipation more difficult.

Even He Tingbo of Huawei admitted that Tau Scaling will not win the "chip war" with the USA overnight. "Given all the various restrictions, we have found some fairly good solutions. I can confidently say that our solutions for mobile computing and AI computing will be competitive in the next ten years," she said. At least.