Semiconductor Testing in the AI Era Why a Targeted Test Distribution is Necessary

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The end of Moore's Law and the boom in AI accelerators require radically new testing strategies. By implementing a targeted test distribution that starts at the wafer level and extends to system-level testing, costs can be reduced and the quality of complex 3D packages ensured.

The rapid proliferation of artificial intelligence (AI) is significantly driving the growth of the semiconductor market. Analysts now predict that it will reach a market volume of one trillion US dollars within this decade. A substantial share of semiconductors will be accounted for by GPUs used in data centers for AI workloads.

Fueled by strong and sustainable investments from hyperscalers, high-performance computing (HPC) and AI data centers are expected to account for a significant share of the overall market. The reason for this growth is the steadily increasing demand for computing power: the training requirements of generative AI models have quadrupled annually since 2018, measured in floating point operations per second (FLOPS).

In addition, semiconductors are increasingly being used in consumer-oriented AI applications, including AI-enabled PCs, smartphones, artificial reality systems, autonomous taxis, and humanoid robots.

Increasing Testing Challenges

The increasing complexity of AI-focused semiconductor devices poses significant challenges to semiconductor testing processes. The number of transistors continues to grow sharply, leading to a corresponding increase in the scope of structural and functional testing.

Power consumption has become one of the most critical limiting factors in test environments. The power requirements of modern components are rising rapidly, demanding that automated test systems (ATE) provide very high currents with precise control and high measurement accuracy. Power supplies for high-performance components must be flexibly scalable, support ganging operation, and ensure consistent performance even under dynamic load conditions. The higher power levels also require advanced protection mechanisms as well as more detailed voltage and current profiling to ensure both component safety and the contact integrity of the test interface.

Increasing Test Performance

Thermal management is also becoming critically important. With increasing test outputs of several kilowatts, active thermal control (ATC) is increasingly required. This applies both at the wafer level and in die-level and package tests. Effective thermal management requires real-time monitoring of power consumption and temperature as well as predictive AI functions that can detect thermal deviations early and proactively counteract them.

Packaging trends further exacerbate these challenges. Advanced 3D packages and multi-chiplet designs are continuously growing in size, significantly complicating both component handling and multisite testing. Larger sockets require more space on test boards, thereby increasing the complexity of ATE resource integration. With the increasing integration of optical functions, the use of integrated electro-optical test solutions becomes necessary. This requires the provision of optical measurement technology across all test stages: from wafer probing to final testing.

Increased Effort in Test Engineering

The provision of the required test resources while shortening the time-to-market for complex components demands an accelerated test engineering effort. This includes support for chiplet architectures, including the simultaneous testing of heterogeneous and homogeneous cores on the same substrate. Furthermore, test encryption will be necessary to protect intellectual property (IP) in multi-vendor environments. Artificial intelligence will play a central role in this process, for example, in code generation and debugging, as well as in combining test processes to increase testing parallelism and reduce test time.

The increasing complexity will significantly shape the test workflow. By the end of this decade, GPUs will each integrate up to one trillion transistors, while AI clusters will consist of up to one million GPUs. As the test scope scales with the number of transistors, testing must meet increasingly stringent defect rate per million (DPPM) requirements. The production test process will require multiple test insertions, starting with die-level testing and extending through burn-in and system-level testing (SLT) to optical tests.

To prevent the total test time from becoming disproportionately long, optimized test insertions are required that reduce both the cost of test (COT) and the time to market (TTM). It will be crucial to execute the respective test contents at the appropriate test stage. This can be supported by seamless portability of test contents, enabling tests to be flexibly shifted from one test insertion to the next. The result is an efficient test distribution that optimally balances DPPM, time to market (TTM), and cost of test (COT).

Flexible Shifting of Test Content

In the era of increasing complexity, test contents are in motion with the aim of optimizing test distribution and achieving the required quality goals. Early test stages focus on identifying Known Good Dies and enabling intelligent assembly of multi-die packages. This minimizes material losses and avoids the costs of packaging defective components. Later test stages focus on ensuring system reliability and detecting defects that only occur under real operating conditions. Figure 1 provides an overview of this process, spanning from validation to system-level testing (SLT).

The so-called Shifting Left, as shown in Figure 2, can significantly increase yield. Since, for example, HBM and CoWoS packaging account for around 70 percent of total costs, it is crucial to shift test contents early to the wafer and die level. The goal is to identify Known Good Dies and perform die matching, ensuring that only tested and compatible functional components are combined in 2.5D/3D packages. This helps reduce costs and avoid unnecessary material usage. At the same time, thermal control and system-related test scenarios are increasingly being implemented in earlier test stages.

The shifting of tests to the right, meaning the execution of tests after packaging, as shown in Figure 3, improves test quality by further reducing DPPM values before the product is delivered. System-level test environments can uncover defects caused by software interactions, timing deviations, or thermal stresses that are not visible at lower test stages. Although these tests can be time-consuming, strategies with high parallelization help effectively limit the impact on overall throughput.

The integration of optical tests, as shown in Figure 4, adds additional insertions to the test process, including tests of photonic components and combined verification of electro-optical modules. In these cases, test contents must also be shifted both left and right to ensure that individual components as well as integrated subsystems meet the required quality and performance standards prior to final assembly.

A Conclusion

The era of AI-driven complexity is redefining test distribution strategies to meet the sharply increasing demands on test scope. Effective testing today requires large amounts of test data and the ability to analyze this data and derive real-time decisions throughout the entire test flow. Furthermore, high electrical power levels and active thermal control (ATC) are now necessary across all test insertions.

To effectively meet these requirements, automated test systems (ATE) are evolving from pure fault detection systems to solutions for system-level validation, supported by AI-based software tools. An optimal test distribution that equally fulfills quality goals, time-to-market (TTM), and cost of test (COT) requires close collaboration of technology partners across the entire semiconductor ecosystem. 

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*Fabio Pizza is Business Segment Manager at Advantest Europe.