Semiconductor manufacturing TSMC prepares A16 process technology, SoW and more

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At the North America Technology Symposium, the executives of chip manufacturer TSMC presented the technologies for the near future that will be implemented by the company. These include the A16 technology for 1.6 nm chips, System-on-Wafer as a packaging technology, and the potential advantages of a back-brick power solution.

Taiwan Semiconductor Manufacturing Company, TSMC, is famously one of the largest and leading companies in the semiconductor industry. As such, the corporation drives technological innovations in order to secure and expand its pioneering role. TSMC organizes several symposia each year, providing a platform for developers, researchers, entrepreneurs, and more to exchange ideas.

One of these symposia, the thirtieth of its kind in North America alone (TSMC North American Technology Symposium), took place on April 24, 2024 and TSMC officials used the event to discuss numerous technologies that will be introduced in the company's chip production in the coming years. The most exciting is TSMC's A16 technology for advanced 1.6-nm chips, which uses nanosheet transistors and a backside power supply called Super Power Rail.

A16: Expensive and different?

Nanosheet transistors are also being used in TSMC's soon-to-begin 2-nm processes (N2, N2P and N2X). Another exciting innovation for the 1.6-nm processes is an advanced network for power supply on the back side called Super Power Rail, which was specifically designed for artificial intelligence and HPC. The combination of Super Power Rail architecture and nanosheet transistors is expected to go into production in 2026 and promises a lot to future customers.

From TSMC's perspective, the A16 process technology is expected to improve logic density and performance, as the routing resources on the front are dedicated to signals. "Compared to TSMC's N2P process, the A16 offers an eight to ten percent speed increase at the same Vdd, a 15 to 20 percent reduction in power consumption at the same speed, and up to 1.10 times improvement in chip density for data center products." The industry is expecting a seven to ten percent increase in transistor density.

Backside Power Delivery Network (or short BSPDN) will be implemented in future process technologies to improve transistor density and power supply, which in turn increases performance. TSMC's Super Power Rail connects the backside power supply network with the transistors, reducing resistance for maximum performance and energy efficiency. From a production perspective, this is said to be one of the most complex BSPDN implementations and more complex than Intel's Power Via.

"Possibly, TSMC decided against backside power supply for the N2P and N2X process technologies, as this would significantly increase production costs. By now offering a 1.6 nm node with GAA nanosheet transistors and SPR, as well as a 2 nm node with GAAFETs (Gate-All-Around Field-Effect Transistor), they are not directly competing with each other but offer different advantages for different customers," analyzes Anton Shilov from Tom's Hardware.

N4C manufacturing technology and System-on-Wafer

Also announced was the N4C manufacturing technology, an extension of the existing N4P production, which comes with a reduction in die costs of up to 8.5 percent and less adoption effort. Volume production is planned for 2025. "N4C offers efficient base IP and design rules that are fully compatible with N4P technology."

In addition to CoWoS (Chip on Wafer on Substrate) as a packaging technology for ICs and System on Integrated Chip (SoIC) as a 3D stacking method, as well as their combination to form an integrated System-in-Package (SiP), TSMC wants to offer a new option with System-on-Wafer (SoW). This allows a large number of dies to be placed on a 300mm wafer, enabling more computing power and less space usage.

"TSMC's first SoW offering, a pure logic wafer based on the Integrated Fan-Out (InFO) technology, is already in production. A chip-on-wafer version using CoWoS is expected to be ready in 2027 and will enable the integration of SoIC, HBM and other components. This results in a high-performance system at the wafer level, its computing power comparable to that of a server rack in a data center or even an entire server," promises TSMC.

Stacking and packaging

Not enough of the announcements from the North America Technology Symposium. TSMC is developing the "Compact Universal Photonic Engine" technology (COUPE) to support the explosive growth of data transmission in the wake of the AI boom. COUPE uses the SoIC-X chip stacking technology to stack an electrical chip on a photonic one. This offers the lowest impedance at the chip-to-chip interface and higher energy efficiency than traditional stacking methods. TSMC plans to qualify COUPE for small form factor connectors by 2025 and drive integration into CoWoS packaging as Co-Packaged Optics (CPO) by 2026 to bring optical connections directly into the package.

And in the automotive industry, TSMC continues to focus on developing solutions for Advanced Packaging to meet the need for more computing power that meets the safety and quality requirements of the road. TSMC is developing InFO-oS and CoWoS-R solutions for applications such as Advanced Driver Assistance Systems (ADAS), vehicle control, and vehicle central computers, targeting AEC-Q100 Grade 2 qualification by the fourth quarter of 2025. All information is available in the TSMC announcement. (sb)