TSMC Announces A14 Manufacturing Process for 2028

1.4 Nanometer Process Still Without High-NA EUV TSMC Announces A14 Manufacturing Process for 2028

2025-05-05 From Sebastian Gerstl | Translated by AI 3 min Reading Time

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At the North America Technology Symposium, TSMC announced the imminent launch of its A14 production process for 2028. Despite 1.4 nm technology, the industry leader intends to forgo high NA-EUV for the time being.

Extended roadmap: Just two years after the recently announced A16 process, TSMC wants to introduce the A14 manufacturing process in 2028 - and still do without high-NA-EUV lithography.(Image: TSMC) — Extended roadmap: Just two years after the recently announced A16 process, TSMC wants to introduce the A14 manufacturing process in 2028 - and still do without high-NA-EUV lithography.
(Image: TSMC)

TSMC presented its new A14 manufacturing process at the North America Technology Symposium. Series production of chips using this 1.4 nanometer process is set to start in 2028. The company was very confident about the development; the development status is already well advanced.

With this announcement, TSMC has steadily expanded its roadmap for the expansion of its manufacturing processes. The introduction of series production using the A16 process is already planned for 2026, with A14 set to follow two years later. In contrast to A16, however, A14 will not yet rely on backside power distribution at this time. Only the A14P variant, planned for 2029, will integrate this technology.

Focus on Efficiency and Density

The A14 process is based on a second generation of gate-all-around nanosheet transistors. Compared to the current 2 nm N2 process, TSMC promises a 15 percent higher clock frequency with the same power consumption or up to 30 percent less energy consumption with the same clock rate. The logic density is set to increase by 20 percent.

Interestingly, TSMC compared A14 directly against its own N2 process, which still relies on FinFET transistors, in its benchmark. The company did not provide a comparison with the A16 process, which will not be introduced until 2026. A16 is said to offer a performance increase of eight to ten percent compared to N2P at the same voltage. The "NanoFlex Pro" platform will be introduced as a new standard cell and IP basis to further improve optimization at chip level.

On the nomenclature of manufacturing processes

The name of the A14 manufacturing process is intended to allude to a structure size of 1.4 nanometers - analogous to the 18A designation at Intel. However, even if the name suggests a linear reduction in structure width, in practice the nomenclature of these processes no longer refers to a directly measurable geometric size in the true sense. Instead, the naming in the industry increasingly serves as a rough technological classification within a roadmap - comparable to a generation designation.

The actual performance of a production process is determined by a large number of technical parameters. These include the minimum line width and spacing (pitch), the number of transistors per square millimeter (logic density), as well as specific performance indicators such as energy efficiency, switching speed and thermal behavior. The ability to integrate complex transistor architectures such as gate-all-around (GAA) also plays a key role. Together, these factors are much more meaningful than a nominal "nm value".

In addition, scaling has different effects in different chip areas. While logic blocks are easy to shrink, SRAM cells are comparatively more difficult to reduce in size. The "functional density" of a chip - i.e. how many usable functions can be realized per area - therefore varies greatly between different manufacturers and processes. Accordingly, process evaluation via benchmarks, performance data and energy consumption is becoming increasingly important compared to traditional measures such as structure size alone.

Waiver of High-NA-EUV

Noteworthy: TSMC also mentioned at the North America Technology Symposium that it will continue to rely on low-NA-EUV lithography with multipatterning for the A14 process. While Intel already relies on high-NA-EUV technology in its 18A process, this is not expected to play a role at TSMC for the time being.

The main reason is of an economic nature, TSMC stated: A high-NA EUV scanner from ASML costs around 380 million US dollars - more than twice as much as a conventional EUV system. For cost reasons, TSMC wants to rely instead on existing technologies with established yields and longer but manageable process times and further optimize them.

However, the planned A14P variant and the later high-performance version A14X could be considered as candidates for the use of high-NA-EUV in the future. However, TSMC does not currently see any urgent need - also because the N2 process will already go into volume production in 2025 and, according to the company, will achieve high yield values. TSMC is thus pursuing a cost-optimized, risk-conscious path: no technology introduction at any price, but a well-founded consideration of feasibility, market maturity and economic benefits. (sg)

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