Semiconductor Components Scaling Monolithic CFETs Across Multiple Logic Technology Nodes

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New Transistor Architecture: Monolithic CFETs Could Revolutionize Semiconductor Manufacturing. Imec has now experimentally proven that scaling for A7, A5, and A3 logic nodes is possible.

In recent years, significant advances have been made in developing process flows for monolithic CFET device architectures (mCFET). However, the semiconductor industry may only be ready to adopt this disruptive transistor architecture if it can be implemented across several successive technology nodes.

Imec conducted a DTCO (Design-Technology Co-Optimization) study to identify the performance-enhancing factors necessary to support aggressive area scaling of mCFET device architectures for A7, A5, and A3 logic nodes.

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For the A3 node, hybrid channel alignments for n- and pMOS transistors are required. The research institute has experimentally demonstrated the key process module that enables the integration of heterogeneous channels in an mCFET: the embedded middle dielectric isolation.

CFET: Significantly Reduce the Size of Logic Cells

Complementary FET (CFET) device architectures are expected to replace gate-all-around (GAA) nanosheet transistors in the roadmap for logic technologies. In a CFET device, n- and pMOS transistors are stacked on top of each other, eliminating the n-p separation from the considerations regarding standard cell height for the first time. Thus, CFET device architectures have the potential to significantly reduce the size of logic standard cells, provided they can be combined with advanced technologies for contacting and powering the transistors.

Of all possible integration processes, monolithic CFET is considered the least disruptive - it offers the fastest way to introduce CFET in industrially relevant dimensions. In monolithic integration, the vertical device structure with common top and bottom gates is structured and processed in a single sequence of process steps.

The vertical stacking of layers poses various challenges, which is why CFET-specific modules are required to enable vertical isolation in critical areas of the stack cross-section. An example of this is the MDI (Middle Dielectric Isolation) module, which provides isolation between the top and bottom gates [1]. This allows different threshold voltages to be defined for the upper and lower components.

Recently, significant progress has been made in demonstrating the critical building blocks for a 300 mm mCFET integration flow. At VLSI 2024, the Belgian researchers reported an mCFET device with MDI module compatible with an inner spacer - a nanosheet-specific feature that isolates the gate from the source/drain (S/D) [2]. At IEDM 2024, the Belgian scientists experimentally demonstrated a functional mCFET with direct backside contact to the S/D of the bottom pMOS device [3].

Imec expects to introduce the mCFET device architecture in the A7 node of the logic technology roadmap when mCFET takes over the successor role of the Outer Wall Forksheet (46285001). The latter is expected to extend the nanosheet-based logic roadmap to the A10 node in anticipation of mCFET being ready for volume production.

Extending mCFET to Other Nodes: A Topic for the Industry

At the circuit level, imec proposed the double-row CFET architecture as the best way to integrate mCFETs into a standard A7 cell [4]. A double-row CFET standard cell contains two rows of stacked devices with a common vertical signal between them and "USS" voltage walls at the cell boundary. At IEDM 2024, a DTCO study demonstrated how this double-row CFET architecture offers the best trade-off between manufacturability and area efficiency for the A7 technology node.

However, the industry has always been reluctant to switch to a new component architecture, as this entails huge investments in tools and additional risks. For a successful transition, it is important that the new architecture can be used across different nodes.

The researchers therefore continued their DTCO study to investigate the scalability of the double-row mCFET in subsequent technology nodes.

To evaluate the PPA (power performance area) metrics at the circuit level, the behavior of a 15-stage ring oscillator (i.e. an RO with 15 mCFET-based inverters) was simulated. The RO was implemented using smaller and smaller standard cell layouts corresponding to the specifications of nodes A7, A5 and A3.

To support scalability, the performance of the RO must be maintained across all nodes while adhering to a limited power density budget. An important metric for performance evaluation is the frequency of the RO, expressed as a ratio of effective driver current to effective capacity.

Performance Booster: Parasitic Capacitance, Forksheet Architecture, M0 Busbar and Hybrid Channels

As the standard cell dimensions decrease, the layer widths of the individual CFET channels also decrease, reducing the effective drive current and increasing the parasitic capacitance. Therefore, power amplifiers are required to balance these parameters and maintain iso-power across all nodes while limiting the increase in power density. The DTCO study presented at IEDM 2025 shows which amplifiers are required for each node to achieve the ambitious area scaling targets [5].

For the A7 node, RO performance comparable to an N2 nanosheet node can be achieved by further minimizing the parasitic capacitance of the gate. This can be achieved by reducing the gate area and the conductor area facing the gate. Optionally, moving the power wall of the double-row CFET to the center of the line (MOL) - resulting in an M0 power rail - can provide an additional advantage.

Scaling to the A5 node requires the introduction of an outer-wall forksheet architecture. So far, the forksheet architecture has been proposed as an extension of nanosheet devices [6], but its architecture is fully compatible with CFET designs. The wall-load approach - characteristic of the outer-wall forksheet variant - is interesting as it increases the channel voltage and thus increases the drive current of the CFET device.

The lower gate extension - enabled by the common n-n or p-p wall of the forksheet - reduces the parasitic gate capacitance. Even more benefits are achieved by implementing an omega-shaped gate that more effectively encloses the channel.

The A3 node requires an additional power booster in addition to the omega gate outer wall forksheet and the M0 busbar. The effective driver current can be further improved by introducing hybrid channel alignments. Tuning the channel alignment affects the mobility of the carriers, with the optimal alignment being different for n-type and p-type devices.

It should be noted that the optimal choice also depends on whether (and to what extent) a preload is introduced into the channel. The imec team has evaluated various channel orientations, with the optimum combination increasing the driver current by up to 20%. The associated increase in power density can be compensated for by equalizing the channel width.

Embedded MDI Module for Hybrid Channel Alignments in an A3 mCFET Process Flow

At IEDM 2025, the Belgians experimentally presented the key module that enables the integration of channels with different orientations for the upper nMOS and lower pMOS devices in an mCFET process flow: the embedded MDI module [7].

The production process for manufacturing the eMDI begins with a carrier and a donor wafer, on which the CFET-specific stacks of Si and sacrificial SiGe layers for the lower and upper channels are epitaxially deposited. These epitaxial stacks are then bonded together again using wafer fusion bonding.

The SiCN bonding dielectric becomes the embedded MDI single film of the mCFET device architecture and insulates the bottom and top parts. After these steps, processing of the mCFET is completed using the conventional mCFET workflow, including nanosheet patterning, Si fin exposure, gate and inner spacer formation, bottom and top S/D epitaxy, and replacement metal gates.

Imec has successfully integrated this eMDI module into a complete mCFET flow and demonstrated functional top devices with different channel orientations: Si top nFETs in (100) orientation, Si top pFETs in (100) and (110) orientation. The top devices were manufactured with front-side connectivity.

The integration process was then extended to include a direct rear contact to the mCFET base component. The CFET team demonstrated functional mCFET devices with an integrated eMDI module, a (100) Si top nFET connected from the front and a (110) Si pFET with direct backside contact.

eMDI: Heterogeneous Channels, Simplified MDI Process Flow, Simpler Si/SiGe Epi Growth, More Stacked Si Channels

The eMDI module offers several advantages over an earlier version of the MDI module, which imec refers to as replacement MDI or rMDI [1]. With rMDI, the active Si/SiGe epi stack is converted into a high Si/SiGe1/SiGe₂ multilayer stack. Later in the process, the sacrificial SiGe1 layers are replaced by the gate working metals and the high SiGe₂ layers are converted into the MDI dielectric.

The main difference between the two approaches lies in the initial design of the substrate. In the case of eMDI, mCFET processing starts with an advanced bonded substrate in which the MDI module is already embedded. The use of separate wafers for growing the active n- and pMOS epi stacks before the first bonding enables the integration of heterogeneous channels optimized for maximum n- and pMOS performance. These can be channels with different orientations - as shown in this study - but also channels with different voltages and even different materials for n and p.

Other advantages include reduced process complexity and simpler epi steps: eMDI avoids the deposition of the complex Si/SiGe1/SiGe₂ multilayer stack and the replacement of the dummy SiGe₂ layers with a dielectric. By growing the epi-stacks on two separate wafers, more Si channels can also be integrated before relaxation of the layers occurs during epi-growth - increasing design flexibility. The novel MDI module can be integrated into any mCFET baseline with minor changes to the mCFET flow.

Various Channel Materials, Embedded Dielectric Insulation Module on the Underside

Imec is currently optimizing the critical modules of the eMDI-based mCFET flow with different channel orientations. Future work will extend the proposed scheme to integrate different channel materials for n and p, i.e. Ge for pMOS and Si for nMOS.

In addition, imec's CFET team intends to use a similar "embedded" approach to integrate Bottom Dielectric Isolation (BDI), a process module required to isolate the S/D epitaxy from the substrate.

The use of an eBDI approach based on layer transfer by wafer bonding should facilitate the integration of the backside interconnect compared to today's replacement BDI (rBDI). In addition, the eBDI approach offers more freedom in the choice of BDI material. One option is to use a highly thermally conductive material, which could address concerns about the thermal reliability of mCFETs.

Conclusion: Imec has used a DTCO study to identify the performance-enhancing factors required to support intensive miniaturization of mCFET device architectures across multiple technology nodes. While minimizing parasitic gate capacitance is critical for the A7 node, the outer-wall forksheet with omega-shaped gate and an M0 busbar are introduced for the A5 and A3 nodes.

For A3, the additional introduction of heterogeneous channels optimized separately for p and nMOS will be critical to maintain performance and power density at maximum scaled standard cell dimensions. An eMDI module is the key technology for integrating heterogeneous channels into an mCFET flow. This has been experimentally demonstrated on mCFET devices with different channel orientations for nMOS and pMOS top devices.

This work was made possible in part by the NanoIC pilot line. The acquisition and operation are jointly funded by the Chips Joint Undertaking through the European Union's "Digital Europe" (101183266) and "Horizon Europe" (101183277) programs and by the participating countries Belgium (Flanders), France, Germany, Finland, Ireland and Romania. (kr)

Literature

[1] ‘Towards a process flow for monolithic CFET transistor architectures,’ imec reading room;

[2] ‘Monolithic complementary field effect transistors (CFET) demonstrated using middle dielectric isolation and stacked contacts,’ S. Demuynck et al., VLSI 2024;

[3] ‘Monolithic-CFET with direct backside contact to source/drain and backside dielectric isolation,’ A. Vandooren et al., IEDM 2024;

[4] ‘Imec proposes double-row CFET for the A7 technology node,’ imec press release;

[5] ‘Multi-node scaling potential of monolithic CFET,’ S. Yang et al., IEDM 2025;

[6] ‘Outer wall forksheet to bridge nanosheet and CFET device architectures in the logic technology roadmap,’ imec reading room;

[7] ‘Hybrid channel monolithic-CFET with Si (110) pMOS and (100) nMOS,’ A. Vandooren et al., IEDM 2025.

*Sheng Yang received her Master's degree in Photonics Engineering from Ghent University in 2016 and her PhD in Photonics Engineering from the same university in 2023. She has been working as a researcher at imec since 2021, focusing on Design and Technology Co-Optimization (DTCO).
 

*Anne Vandooren received her Master's degree in Electrical Engineering from the Université Catholique de Louvain (UCL) in Belgium in 1996 and her PhD in Electrical Engineering from the University of California, Davis in 2000. From 2000 to 2007, she was a senior researcher at Motorola/Freescale, working on the integration of FDSOI and FinFET technologies. She joined imec in 2007 as a Principal Member of Technical Staff. In this role, she focuses on the development of novel CFET architectures, including monolithic and sequential approaches as well as backside interconnects.
 

*Geert Hellings received his PhD in Electrical Engineering from KU Leuven in Belgium in 2012. He joined imec in 2006 and worked on III-nitride based detectors, high mobility transistors, ESD and reliability before moving to the Design Technology Co-Optimization program in 2020. In 2022, he became Program Director for the integrated DTCO program. Currently, his research focuses on compute density scaling for CFET technologies and beyond within imec's Cross-Technology Co-Optimization program.
 

*Naoto Horiguchi is Director of CMOS Device Technology at imec. He graduated from the University of Tokyo in Japan with a degree in Applied Physics in 1992. He has worked at Fujitsu and the University of California at Santa Barbara, where he was involved in the development of semiconductor nanostructure devices and advanced CMOS technology. He joined imec in 2006, where he has been involved in the research and development of advanced CMOS devices together with worldwide industry partners, universities and research institutes. He is currently focusing on scaling down CMOS devices to the 1nm technology node and beyond.