Microcontroller The advantages of Raspberry Pi Pico 2 over Pico 1

From Margit Kuther | Translated by AI 6 min Reading Time

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With the Pico series, Raspberry Pi launched its microcontroller boards. Raspberry Pi Pico 2 looks similar to its predecessor but offers significantly more thanks to the RP2350 chip, such as alternatively usable RISC-V cores. More details are revealed in this article.

Image 1: The microcontroller board Raspberry Pi Pico 2 is based on the RP2350.(Image: Raspberry Pi)
Image 1: The microcontroller board Raspberry Pi Pico 2 is based on the RP2350.
(Image: Raspberry Pi)

The second-generation microcontroller board, Raspberry Pi Pico 2, is based on the RP2350 chip: highlights include two RISC-V cores, two M33 processor cores clocked at 150 megahertz, 4 MB instead of 2 MB of flash memory, new security features, and improved interface capabilities.

For the Pico 2, this means a significant increase in performance and functionality, while maintaining hardware and software compatibility with earlier members of the Pico series. It is mechanically and electrically compatible with the original Pico design. The Pico 2 is available from about 5 euros.

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RP2040: The Microcontroller for Engineers

In 2021, the original Raspberry Pi Pico and the RP2040 microcontroller, which is also available solo, were introduced. "In the three and a half years that have passed since then, we have sold nearly four million units of the Pico and its Wireless sibling, the Pico W," said Eben Upton, Chief Executive of Raspberry Pi Trading.

"The RP2040 itself has found a home in countless third-party development boards and in OEM products ranging from pinball tables to synthesizers. However, there were features on our list that didn't make it the first time: on-chip memory, power-saving idle states, packaging options. And there were new features requested by the numerous RP2040 users: faster cores, more RAM, code protection."

RP2350 - More Performance Yet Still Cost-Effective

About two years ago, with the RP1 I/O Controller for the Raspberry Pi 5, the Raspberry Pi chip team began work on the RP2350. This is a much more sophisticated design than the RP2040, featuring:

  • Two Arm Cortex-M33 cores at 150 MHz, with floating point and DSP support,

  • 520 KB on-chip SRAM in ten simultaneously accessible banks,

  • a comprehensive security architecture based on Arm TrustZone for Cortex-M, which includes: support for signed booting, 8 KB on-chip antifuse one-time programmable (OTP) memory, SHA-256 acceleration, a true hardware random number generator (TRNG),

  • an on-chip switch-mode power supply and a low quiescent current LDO,

  • twelve upgraded PIO state machines,

  • a new HSTX peripheral for high-speed data transmission,

  • Support for external QSPI PSRAM.

While the RP2040 has only one QFN56 package option measuring 7 mm x 7 mm, the RP2350 offers a choice: a QFN60 package (RP2350A) measuring 7 mm x 7 mm with 30 GPIOs or a QFN80 package (RP2350B) measuring 10 mm x 10 mm with 48 GPIOs, along with variants of each featuring 2 MB stacked-in-package QSPI flash (RP2354A and RP2354B).

Raspberry Pi has stayed true to its affordable roots: "Although our silicon die now measures an extravagant 5.3 mm², compared to 2.7 mm² for the RP2040, the RP2350A is only intended to be ten cents more expensive, costing about $0.80 in reels of 3,400 units or about $1.10 in single quantities. RP2350B is expected to cost ten cents more than RP2350A, while the RP2354 variants will be just twenty cents more. The RP2350 should be available in large quantities before the end of 2024," said Eben Upton.

Alternatively, RISC-V usable

"Although we have been a member of RISC-V International for many years, we have never had the opportunity to deliver a RISC-V Raspberry Pi product," said Eben Upton. "But now, the RP2350 chip in the Pico 2 can alternatively run RISC-V, thanks to a bonus feature": Luke Wren, Principal Engineer in the Raspberry Pi Chip Team, developed the Hazard3. This consists of two open-hardware Hazard3 RISC-V cores that can be used at boot instead of the Cortex-M33 cores.

"Our boot ROM can even automatically detect the architecture for which a second-stage binary has been created and reboot the chip into the corresponding mode. All functions of the chip, apart from a handful of security features and the double-precision floating-point accelerator, are available in RISC-V mode," says Eben Upton.

Hazard3, published on Github, is a highly optimized three-stage pipeline processor that implements the RV32I instruction set and a large collection of standard extensions to enhance performance and code density. By adding Hazard3 to the RP2350, Raspberry Pi aims to give software developers the opportunity to experiment with the RISC-V architecture in a stable, well-supported environment. Eben Upton recommends that those interested should "look at Luke's historical contributions on Twitter/X, which detail the development process."

Signed boot process in the RP2350

The cornerstone of the RP2350 security model is the signed boot process. When security is enabled, a binary can only be booted if it is signed with a private key, with a hash of the corresponding public key stored in the OTP (One-Time Programmable memory). This prevents an attacker from running arbitrary code, significantly complicating any attempt to extract the contents of the OTP, including the cryptographic keys used to protect the code.

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Collaboration with the Trusted Firmware project and Google

Raspberry Pi has collaborated with the Trusted Firmware project to establish the RP2350 microcontroller as the reference hardware platform for the Trusted Firmware M 2.1.0 Long Term Support Release. TF-M provides a reference implementation for PSA Certified on Arm-v8-M chips, enabling developers to protect devices against common attacks. Additionally, the RP2350 is being tested by a certified, independent laboratory with the goal of achieving PSA Certified Level 2.

There is also a collaboration with Google to bring to market the Pigweed SDK with native support for the Pico 2. Pigweed's middleware libraries have already been shipped in millions of devices, including Google's own Pixel devices and Nest thermostats. The Pigweed SDK simplifies the use of these components in developing projects for the Pico 2.

Additional technical details of the Pico 2

The RP2040 in the Pico 1 has a built-in linear regulator that steps down 3.3 V to 1.1 V for the processor core. The RP2350 features an onboard switching power supply that performs the same task but more efficiently. Nick Francis, ASIC Technical Director at Raspberry Pi, comments: "Raspberry Pi has moved from a regulator to a switcher in the Pico 2 because regulators are inherently less efficient under load."

"We have therefore changed our core power regulator—it is actually a combination unit that includes a small regulator for power-saving modes up to 1 mA, when most of the chip is off and we are waiting for the wake-up. And when we power up the core, we switch to a switching power supply that can deliver up to 200 mA—more than the RP2040, as the chip is larger and therefore has a higher peak current. The switching power supply is more efficient than the regulator used in the RP2040."

Raspberry Pi has added a third PIO (Programmable Input Output) block to the Pico 2, thus including four more state machines, and continues to use the 40-nm process from TSMC. "Maintaining the same process means that we can reuse some of the IP and knowledge that we gathered with the RP2040, as well as with the RP1 (the first in-house chip from Raspberry Pi, used in the Raspberry Pi 5. Therefore, we reused cell libraries, memory, ADC, PLL, and USB PHY from the RP2040."

Wireless Pico 2 expected to be available later in 2024

Raspberry Pi plans to launch a wireless variant, the Pico 2 W, featuring the same 43439 modem from Infineon as in the Pico W, as well as versions of the Pico 2 and Pico 2 W with pre-installed 0.1-inch connectors, all before the end of the year.

Hardware specification of the Pico 2

  • Form factor: 21 mm x 51 mm,

  • CPU: Two Arm Cortex-M33 or two RISC-V Hazard3 processors at 150 MHz,

  • Memory: 520 KB on-chip SRAM; 4 MB on-board QSPI flash,

  • Interfaces: 26 multi-purpose GPIO pins, including three that can be used for ADC,

  • Peripherals: 2 × UART, 2 × SPI controllers, 2 × I2C controllers, 24 × PWM channels, 1 × USB 1.1 controller and PHY, with host and device support, 12 × PIO state machines,

  • Input voltage: 1.8-5.5 VDC

  • Operating temperature: -20 to 85 °C

(mk)

This article was first published on our sister website www.ElektronikPraxis.de (German language)