Advanced Packaging Technology Panel-Level Packaging at TSMC: First CoPoS Pilot Line in 2026, Mass Production from 2029

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It has been known for some time that contract manufacturer TSMC is warming up to the idea of using rectangular substrates. The development of panel-level packaging has apparently progressed to the point that the first pilot line is expected in 2026, with mass production starting in 2029.

The world's largest contract manufacturer, TSMC, is further advancing the development of its panel-level packaging technology CoPoS (Chip-on-Panel-on-Substrate), as reported by multiple sources (via Trendforce). Asian media outlets MoneyDJ and Economic Daily News recently reported that a pilot line at TSMC is expected to start as early as 2026. Mass production is planned for 2029.

This step is a response to the growing demands in the field of AI accelerators, especially to the requirements of major customers like Nvidia, which, according to MoneyDJ, is considered the first customer for CoPoS.

Panel-Level Packaging

CoPoS is an advancement of the existing packaging technologies CoWoS-L (for Nvidia and AMD) and CoWoS-R (for Broadcom), designed by TSMC. CoPoS utilizes rectangular substrates instead of round ones for the first time. The panels, measuring 12.2 × 12.2 inches, are expected to offer more usable area per unit, thereby increasing yield and reducing costs. According to those responsible, this presents a decisive advantage in light of the ever-larger chip packages in the AI sector.

The production and handling of rectangular panels require high precision, especially in the placement and connection of the chips. The drawback of round wafers is that a lot of waste is generated at the edges, and the shape does not allow for efficient placement of packages. AI chips are getting larger. Already last year, when CoPoS development at TSMC was still in its infancy, it was expected that only 16 B200 chipsets could be placed on a round 12-inch silicon wafer, compared to 29 H100 or H200 chipsets from Nvidia. In the summer of 2024, unconfirmed sources suggested that TSMC experimented with rectangular wafers measuring 20.1 × 20.3 inches. Current reports indicate that a more compact format of 12.2 × 12.2 inches  has prevailed.

Conversion Becomes Necessary

According to the reports, the AP7 campus in Chiayi (Taiwan) will become the central hub for the new technology. Structured in eight construction phases, Phase 4 is expected to enable large-scale CoPoS manufacturing for the first time. According to MoneyDJ, the previous construction phases are reserved for Apple (WMCM modules) as well as for scaling SoIC processes. The existing CoWoS manufacturing, however, will remain at the AP8 location.

With CoPoS, TSMC is responding not only to the technological demands of growing AI chips but also to economic pressure: traditional wafers are reaching capacity limits with package sizes like Nvidia's B200. Rectangular panels could help alleviate this bottleneck, provided that manufacturing, materials, and equipment can be converted accordingly. (sb)

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