Efficiency Increase Afterwards More Energy-Efficient Microchips Through Component Stacking

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Researchers at MIT, in collaboration with Intel, have developed a new production approach for microelectronics: stacking multiple active components using new materials on the back of a computer chip is expected to drastically reduce the amount of energy wasted during computations.

In conventional circuits, logic components, which perform calculations like transistors, and memory components, which store data, are built as separate units. Data must move back and forth between them, wasting energy.

A novel electronics integration platform developed by MIT researchers is designed to enable the production of transistors and memory components in a compact stack on a semiconductor chip. This avoids much of the energy waste while simultaneously increasing computing speed. This approach is based on a newly developed material with "unique properties," according to MIT, and a precise manufacturing process that reduces the number of defects in the material. As a result, the researchers can produce extremely small transistors with integrated memory that operate faster than state-of-the-art devices while consuming less power than similar transistors.

By improving the energy efficiency of electronic devices, this new approach could help reduce the growing power consumption of computing applications, particularly for demanding tasks such as generative AI, deep learning, and computer vision. "We need to minimize the energy consumption for AI and other data-centric computations in the future, as it is simply unsustainable. We need new technologies like this integration platform to continue this progress," says Yanjie Shao, postdoctoral researcher at MIT and lead author of two papers on these new transistors.

Reversal of A Problem

Standard CMOS chips (Complementary Metal-Oxide Semiconductor) traditionally feature a front-end, where active components like transistors and capacitors are manufactured, and a back-end, which contains wires, known as interconnects, and other metal connections that link the chip's components. However, during data transmission between these connections, some energy is lost, and slight misalignments can impact performance. By stacking active components, the distance data must travel would be reduced, improving the chip's energy efficiency.

Normally, it is difficult to stack silicon transistors on a CMOS chip because the high temperatures required to fabricate additional components on the front side would destroy the existing transistors underneath. MIT researchers have reversed this problem and instead developed an integration technique that allows active components to be stacked on the back side of the chip. "If we can use this back-end platform to incorporate additional active transistor layers, not just connections, it would significantly increase the chip's integration density and improve its energy efficiency," explains Shao.

The researchers achieved this by using a new material, amorphous indium oxide, as the active channel layer of their back-end transistor. The essential functions of the transistor occur within the active channel layer. Due to the unique properties of indium oxide, they can grow an extremely thin layer of this material at a temperature of only about 300°F on the back side of an existing circuit without damaging the front-side device.

Maturation of the Process

They carefully optimized the manufacturing process, minimizing the number of defects in a layer of indium oxide material that is only about 2 nanometers thick. A few defects, known as oxygen vacancies, are necessary for the transistor to switch on, but too many defects prevent it from functioning properly. This optimized manufacturing process enables the researchers to create an extremely small transistor that operates quickly and efficiently, saving much of the additional energy required to switch a transistor between off and on states.

Building on this approach, they also created back-end transistors with integrated memory that are only about 20 nanometers in size. To achieve this, they added a layer of a material called ferroelectric hafnium zirconium oxide as the memory component. These compact memory transistors demonstrated switching speeds of just 10 nanoseconds, reaching the limit of the team's measurement instruments. This circuit also requires much lower voltage than similar devices, reducing power consumption. Because the memory transistors are so tiny, the researchers can use them as a platform to study the fundamental physics of individual units of ferroelectric hafnium zirconium oxide.

"If we understand the physics better, we can use this material for many new applications. The energy consumption is very low, and it offers us a lot of flexibility in device design. This could really open up many new paths for the future," says Shao. The researchers also collaborated with a team from the University of Waterloo to develop a model for the performance of the back-end transistors, which is an important step before these devices can be integrated into larger circuits and electronic systems.

In the future, they aim to build on these demonstrations by integrating back-end memory transistors into a single circuit. Additionally, they plan to improve the performance of the transistors and investigate how the properties of ferroelectric hafnium zirconium oxide can be controlled even more precisely.

"Now we can build a platform for versatile electronics on the back side of a chip, enabling us to achieve high energy efficiency and many different functions in very small devices. We have a good device architecture and good materials to work with, but we need to keep innovating to uncover the ultimate performance limits," says Shao.

This work is partially supported by the Semiconductor Research Corporation (SRC) and Intel. The manufacturing was carried out at the MIT Microsystems Technology Laboratories and MIT.nano facilities.

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