MIPI Introduces I3C Basic v1.2 With A New Structure

New Interface Version MIPI Introduces I3C Basic v1.2 With A New Structure

2025-08-15 From Manuel Christa | Translated by AI 2 min Reading Time

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I3C Basic v1.2 is here and reorganizes the entire standard: mandatory and optional features are clearly separated. The two-wire interface reduces pin count and integration effort, offers 11.1 Mbit/s in standard mode, and reaches up to 100 Mbit/s in HDR modes.

MIPI I3C Interop Workshop in Munich(Image: Angelika Güc) — MIPI I3C Interop Workshop in Munich
(Image: Angelika Güc)

The MIPI Alliance elevates the Utility and Control Bus interface I3C Basic to version 1.2. The specification now separates mandatory and optional features into separate chapters. Manufacturers can specifically implement only the required features without unnecessary overhead. This saves integration effort and reduces costs.

I3C builds on the experience of I2C, SPI, and UART, reducing the number of lines, simplifying timing, and enabling in-band interrupts. The bus typically operates at 11.1 Mbit/s and switches to 100 Mbit/s for high-data-rate modes when needed. This shortens diagnostic times, accelerates sensor pathways, and conserves energy in mobile and embedded systems. I3C Basic is the royalty-free subset of the member specification MIPI I3C.

Gallery

MIPI I3C supports options for more powerful modes with high data rates, enabling speeds of over 30 Mbit/s in single-lane mode without compromising energy-efficient design.(Image: Angelika Güc)

MIPI I3C reduces energy consumption for transmitting 1 kB by 5 to 18 times compared to conventional I2C.(Image: Angelika Güc)

Two-Part Specification, Clear Application Paths

What is I3C specifically suitable for? Three main areas are the focus:

Connecting peripherals to processors
System debug and trace
Use as a control sideband bus

Specifically, these include DDR5 memory modules, SSD management, and camera control via the Camera Control Interface (CCI). Since I3C runs on standard CMOS I/O and requires only two lines, pin count and routing complexity on the board are reduced.

In parallel, the ecosystem continues to grow. Drivers are available for Linux and the RTOS Zephyr, along with protocol analyzers, USB host adapters, and dev boards. Microcontroller and sensor manufacturers are producing native I3C blocks in series, and reference implementations shorten the bring-up phase.

Broad Adoption in Existing Standards

Institutions are already firmly integrating I3C Basic: PCI-SIG and NVM Express use it as a modern system management bus, JEDEC incorporates it into the DDR5 sideband bus, and ETSI integrates it into the Smart Secure Platform and UICC. Additionally, a liaison with the DMTF (Distributed Management Task Force) is underway regarding management protocols. This signals that I3C is not merely functioning as a sensor aggregation bus but is also taking on sideband tasks across data centers and client platforms.

"The MIPI I3C ecosystem has grown rapidly in recent years, and we expect this rapid adoption to continue," says Hezi Saar, Chairman of the MIPI Alliance. "Companies have adopted the I3C interface due to its innovative features and significant improvements in performance and energy efficiency compared to older interfaces. I3C offers developers exceptional flexibility, making it suitable for a wide range of products—from smartphones and wearables to systems for data centers."

Additionally, the I/O Bridges working group was recently established: it is defining an "I/Os over I3C" bridge, which is planned for completion by mid-2026. Practical trials took place at the end of June during the Plugfest in Warsaw, linked to Member Meeting #69. Teams from nine companies tested interoperability between controllers and target devices in mixed operation. Those looking to get started can download I3C Basic v1.2 directly from the website and enable the optional chapters as needed. (mc)

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Date: 08.12.2025

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