Advanced Packaging in Chip Design From SoC to Chiplet: Intel's Path to a Modular Future

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Fraunhofer-Institut für Integrierte Schaltungen IIS

Intel Deutschland GmbH

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How Intel is shaping the transition to chiplet systems with EMIB, Foveros and hybrid bonding and why advanced packaging is becoming the key technology for the data center of the future. Housing expert Bernd Waidhas from Intel spoke about this.

Moore's Law has long since lost its significance. Apart from the long-correct prediction that transistors in integrated circuits would double every two years, Gordon Moore made another, but now more topical, statement in the same article:

"It could prove to make more economic sense to assemble large systems from smaller functions, with assembly and connection technologies offering the necessary flexibility."

Although less succinct than the more well-known prediction, the Intel co-founder described the current relevance of packaging technologies in chip development back in 1956. Bernd Waidhas, an expert in package development at Intel, introduced his presentation on advanced packaging with this quote at the Specialist Conference "Chip Development" on April 9, 2025 at Fraunhofer IIS in Erlangen. The most important contents and findings of his presentation are summarized below.

Modular Packaging: The Chiplet Era

However, advanced packaging is more than just a packaging technology: it is becoming the system architecture at package level and therefore the foundation of modern data center chips. This is because classic monolithic designs are increasingly reaching their physical, economic and technological limits. Chiplets that are connected via high-performance interposers and standardized interfaces make it possible to build modular and scalable systems and thus react flexibly to changing requirements in data centers.

At the same time, advanced packaging improves energy efficiency, increases the bandwidth between functional units and allows the integration of a wide variety of process nodes in a small space. As a result, the focus of innovation is increasingly shifting from silicon to packaging - making packaging itself the decisive architectural component of the next generation of chips.

In comparison, monolithic chips continue to offer advantages such as lower power consumption and lower latency, as the components are physically closer together. Monolithic designs are particularly suitable for high-performance applications where tight integration and fast communication between components is required. Despite the clear emergence of modular designs, monolithic chips still dominate.

Chiplet technology offers numerous advantages, including the possibility of targeted disaggregation of functions, improved reusability of intellectual property (IP) and optimization of yield in chip production. However, chiplet integration is also associated with challenges, such as greater design complexity and implementation costs.

Standards for Die-to-Die Connections

Standardized connections between individual dies, so-called die-to-die interconnects, are a decisive factor in the implementation of chiplet architectures. Bernd Waidhas presented in particular the open standard Universal Chiplet Interconnect Express (UCIe), which is being developed primarily by Intel and other industry partners.

UCIe covers various package types and differentiates between standard packages with coarser pitches (100 to 130 µm), advanced packages with interposers (25 to 55 µm) and highly complex 3D packages with hybrid bonding (less than 10 µm). UCIe also offers solutions for the interoperability of chiplets with different pitch sizes, enabling a wide range of possible combinations.

Interposer Technologies: It's the Connection That Counts

With the trend towards more highly integrated chiplet systems, high-performance interposers are becoming increasingly relevant. These connecting elements between chiplets and substrates have undergone significant technological development. While silicon interposers were initially mainly used, for example to connect high bandwidth memory (HBM), RDL (redistribution layer) interposers and organic interposers are now increasingly being used. The latter enable larger dimensions at lower costs and offer better thermal and mechanical performance.

In his presentation, Waidhas also points out the different production methods for these interposers. Depending on the application, chip-first or chip-load processes are used. TSMC, for example, differentiates between CoWoS-R (chip-load) and CoWoS-L or InFO-L (chip-first) in its packaging technologies. Both variants offer different advantages and disadvantages in terms of process control, yield and system integration.

The connecting elements between chiplets and substrates have undergone significant technological development. While silicon interposers were initially mainly used, for example to connect high bandwidth memory (HBM), RDL (redistribution layer) interposers and organic interposers are now increasingly being used. The latter enable larger dimensions at lower costs and offer better thermal and mechanical performance.

(No) Interposer

Intel is pursuing different approaches to packaging with two platforms: EMIB (Embedded Multi-die Interconnect Bridge) realizes a point connection without a full-surface interposer. Small silicon bridges are embedded directly in the substrate. Foveros, a 3D packaging technology that stacks active dies vertically on top of each other, is also used. The combination of both approaches, referred to by Intel as EMIB 3.5D, allows particularly flexible design variants for high-performance multi-die systems.

Waidhas also mentioned EMIP technology (Embedded Multi-die Interconnect without Interposer) in his presentation, in which an active connection chip is embedded directly into the BGA substrate - without a classic interposer. This makes it possible to further simplify the packaging structure and at the same time achieve high signal quality.

Hybrid Bonding: Copper Instead of Solder

Hybrid bonding is a particularly sophisticated approach to connecting chiplets. Unlike conventional soldering processes, the connection is made by direct metallic contact, typically copper-to-copper, without the use of solder. Bernd Waidhas explained the multi-stage process, which includes chemical-mechanical polishing (CMP) to align the surfaces, plasma activation and precise alignment of the dies. Finally, the chips are fused under slight pressure and at elevated temperatures, creating an intermetallic compound that no longer has a visible interface.

Hybrid bonding allows pitch sizes below 10 micrometers and is therefore particularly suitable for 3D stacking applications where high connection densities are required. The technology was originally used in CMOS image sensors, for example by Sony, and is now also increasingly being used in high-performance processors. However, the process is complex and places high demands on production tolerances and thermal management, warns the speaker.

Backside Power Delivery: Power Supply from Below

Another point that Bernd Waidhas addressed in his presentation concerns the future power supply in chiplet systems: so-called backside power delivery. Here, power and signal lines are routed separately - signals at the top, power supply via the back of the chip. This reduces the vertical complexity in the package and enables shorter signal paths. In combination with gate-all-around transistors, which Intel calls RibbonFET, this can lead to more efficient integration and higher performance.

Other suppliers are also already mentioning this technology - but Intel is the first foundry to use it in series production. PowerVia is the name of Intel's rear power supply since the 20A process technology. Intel's successor technology called PowerDirect, which is to be used at 14A, has also been known since the end of April 2024.

Roadmap and Market Potential: 5% of Chips to Account for 50% of Sales

Advanced packaging has long been more than just a production step - it is developing into a key economic and strategic component of the semiconductor industry. According to Yole Intelligence, the global market for advanced packaging will grow from 44.3 billion US dollars in 2022 to 78.6 billion US dollars in 2028 - with an average annual growth rate of 10.6%. Waidhas added in his presentation that, according to the forecast for 2028, only around five percent of chip packages will be accounted for by advanced packaging (unit split). However, due to the higher complexity and added value, the industry expects these technologies to account for more than 50% of revenue (revenue split).

Intel itself sees advanced packaging as a key to future high-performance systems. Among other things, Waidhas presented plans for future chiplet systems with four reticle-sized compute dies and up to 16 HBM4 components. These designs require large-area interposers and place high demands on signal and power supply as well as thermal management.

Conclusion: Recognizing Opportunities, Mastering Complexity

Bernd Waidhas' presentation shows how chiplet-based systems enable new degrees of freedom in system integration. Technological hybrids can reduce development costs in the long term. At the same time, this change requires a high degree of coordination: the selection of suitable interconnect standards, thermal management, mechanical stability and electrical integrity must be carefully coordinated.

"There are of course many ways to create new architectures using these packaging technologies. However, you should think carefully about whether it makes sense for your system or whether you should stick with the SoC. Because of course you also have an overhead due to all the die-to-die connections and you have additional costs due to advanced packaging," warns engineer Waidhas and considers a "multidimensional analysis" to be necessary.

Successful chiplet strategies require not only technical expertise, but also early and close coordination with partners along the value chain. Standardized interfaces such as UCIe, advanced interposer technologies and flexible packaging platforms such as EMIB and Foveros form the basis for this - but are not a sure-fire success:

"Many years ago, there was euphoria at panel discussions where it was said that you could buy chiplets from different companies, combine them in a package and it would work - it's not quite that simple," warns housing expert Bernd Waidhas in his concluding appeal. (mc)