Zollner Elektronik AG wins PCB Design Award 2024 for supercomputing hardware

Component design Zollner Elektronik AG wins PCB Design Award 2024 for supercomputing hardware

2025-02-19 Source: Zollner | Translated by AI 1 min Reading Time

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The award-winning project, a PCIe add-on card for STX accelerator chiplets, impresses with its excellent high-speed and high-density design and is used in data centers for machine learning, climate simulation, and neural networks.

Simulation and layout of PCI lanes: Illustration of signal routing and optimization of trace routing for high-speed data transmission.(Image: Zollner) — Simulation and layout of PCI lanes: Illustration of signal routing and optimization of trace routing for high-speed data transmission.
(Image: Zollner)

For several years, the PCB design group at Zollner Elektronik AG has been engaged in design tasks in the field of high speed/high density. Now, the assembly group has been honored with the PCB Design Award 2024 by the Fachverband Elektronikdesign und -fertigung (FED) at this year's conference. This award, established for the seventh time by the FED, recognizes assembly designers for excellent work every two years.

As part of a project by the Federal Ministry of Education and Research (BMBF), a PCIe add-on card for STX accelerator chiplets was developed, which is used in data centers for weather and climate simulation as well as in the field of neural networks and machine learning. Due to the planned series production, marketability was a focus alongside functionality even for the demonstrator, utilizing the full range of the Research & Development service portfolio.

In addition to the hardware, software for control, diagnostics, and power management was also developed. Challenges included the high switching speeds of PCIe 5.0 (32GT/s) and stable power supply with a point-of-load concept that includes 21 partially separate power supplies. The assembly generates a maximum power loss of 225W, which is dissipated by air cooling. Through energy-saving measures and halving the assembly height, double the number of assemblies could be accommodated in a 19" slot, thereby achieving double the computing power per server rack with less connection power.

Together with the project partners, a requirements specification, the system architecture, and the hardware and software requirements were developed, taking into account all relevant standards. The circuit parts were dimensioned using simulations, the circuit diagram was derived, and the layer stack-up was defined in collaboration with the PCB manufacturers. In parallel with component placement, thermal simulations and the design of the heatsink were initiated.

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