Standard cell architecture Two-row CFET technology for the A7 technology node

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The Belgian research institute imec has unveiled an innovative standard cell architecture for semiconductor manufacturing in a 0.7nm CMOS A7 process. The CFET architecture, consisting of two rows of CFETs with a common interconnect line for signal routing in between, promises process simplification and a significant reduction in logic and SRAM cell area.

The semiconductor industry is making significant progress in the production of (monolithic) CFET components, which are set to replace Gate-All-Around Nanosheets (NSHs) in the logic technology roadmap. The stacking of n- and pFET components promises advantages in terms of power, performance, and area (PPA) when combined with backside technologies for power delivery and signal routing.

Reduced standard cell heights for accommodating transistors in two layers

At the circuit level, however, several options remain open for the integration of CFETs into a standard cell to achieve or enhance the expected PPA advantages. A particular challenge is MOL connectivity (Middle-of-Line), i.e., the connections that link source/drain and gate contacts with the first metal lines (on the front and back sides) and ensure top-to-bottom connectivity for power and signals.

A DTCO study (Design-Technology Co-Optimization) by the Belgian research institute imec comparing standard cell architectures reveals that the double-row CFET offers the optimal compromise between feasibility and area efficiency for A7 logic nodes. This new architecture is based on a base cell where one side of the CFET is optimized for power connections— including a power rail (VSS) to power the upper element from the backside and a direct connection to the backside of the lower element. The other side is optimized for signal connections by providing a middle routing wall (MRW) for the top-to-bottom connection. The double-row CFET standard cell (with two rows of stacked elements) is subsequently formed by mirroring two base cells that share the same MRW for the signal connection (see image).

Area savings of 15 percent in SRAM cells

"Our DTCO study shows that a shared MRW for every 3.7 FETs is sufficient to build logic and SRAM cells," says Geert Hellings, Program Director DTCO at imec. "This allows us to further reduce the standard cell heights from 4 to 3.5 T compared to 'classical' single-row CFETs. This results in a significant area saving of 15 percent for SRAM cells. Compared to SRAMs manufactured, for example, with A14-NSH technology, double-row CFET-based SRAMs enable an area reduction of more than 40 percent, offering another scaling path for SRAMs."

The two-row CFET also leads to a simplification of the process as the MRW trench is shared by two rows of CFET devices. This eliminates the need for an additional high aspect ratio via to connect the upper and lower devices if necessary, thereby reducing the complexity and cost of MOL processing.

"Since the 7nm technology node, standard cell optimization through DTCO has contributed an increasingly significant share to increasing node density, in addition to conventional device scaling," adds Geert Hellings. "For our DTCO study on CFET architectures, we have based it on the process capabilities planned for future CFET fabs to ensure industry-relevant process flows. Furthermore, we are validating our virtual fab concept with technology proof-of-concepts carried out in imec's 300mm cleanroom. This combination of virtual fab and real pilot line activities is a crucial step towards advancing our roadmaps."

At the IEDM, imec also experimentally demonstrated an important component of this double-row CFET architecture: a functional monolithic CFET with direct backside contact to the source/drain of the lower pMOS component. This was achieved through EUV backside patterning, which ensured dense backside power and signal wiring and a tight overlay (<3 nm tolerance) between the front-side generated sourcedrain, backside contact, and subsequent metal layers. (sg)