Chip Cryptography A Shared Digital Fingerprint for Enhanced Chip Security Right from Manufacturing

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Researchers at MIT have developed a new manufacturing technique that gives two chips a common "fingerprint". This allows one chip to authenticate the other directly without having to store important information on a third-party server.

Just as every person has unique fingerprints, every CMOS chip has a distinctive "fingerprint" created by tiny, random manufacturing tolerances. Engineers can use this tamper-proof ID for authentication to protect a device from attackers trying to steal private data.

However, these cryptographic methods usually require secret information about a chip's fingerprint to be stored on a third-party server. This creates security gaps and a need for additional storage space and computing power.

To overcome this limitation, MIT engineers developed a manufacturing process that enables secure, fingerprint-based authentication without the need to store secret information outside the chip.

They split a specially developed chip during manufacture so that each half has an identical, shared fingerprint that is unique to these two chips. Each chip can be used to directly authenticate the other. According to the researchers, this cost-effective method of producing fingerprints is compatible with standard CMOS foundry processes and requires no special materials.

The technology could be useful in electronic systems with limited power consumption and non-interchangeable pairs of devices, such as an ingestible sensor pill and its accompanying wearable patch that monitor the health of the gastrointestinal tract. Using a shared fingerprint, the pill and the patch can authenticate each other without the need for an intermediary device.

"The biggest advantage of this security method is that we don't have to store any information. All secrets always remain securely stored in the silicon. This can provide a higher level of security. As long as you have this digital key, you can unlock the door at any time," says Eunseok Lee, PhD student in Electrical Engineering and Computer Science (EECS) and lead author of a publication on this security method.

Lee is joined in the publication by EECS doctoral students Jaehong Jung and Maitreyi Ashok, and co-senior authors Anantha Chandrakasan, MIT provost and Vannevar Bush Professor of Electrical Engineering and Computer Science, and Ruonan Han, professor of EECS and a member of the MIT Research Laboratory of Electronics. The research results were recently presented at the IEEE International Solid-States Circuits Conference.

"Creating shared encryption keys in trusted semiconductor factories could help overcome the trade-off between more security and more usability in protecting data transmission," says Han. "This work, which is digitally based, is still a first attempt in this direction. We are investigating how more complex, analog secrecy systems can be duplicated - just once."

Exploiting Variations

Although they are supposed to be identical, each CMOS chip differs slightly from the others due to unavoidable microscopic variations during manufacture. These randomnesses give each chip a unique identifier called a physically unclonable function (PUF), which is nearly impossible to replicate. A chip's PUF can be used to ensure security, much like the fingerprint identification system on laptops or doors.

For authentication, a server sends a request to the device, which responds with a secret key based on its unique physical structure. If the key matches an expected value, the server authenticates the device.

However, the PUF authentication data must be registered and stored on a server in order to access it later, which is a potential security vulnerability. "If we don't have to store information about these unique randomizations, the PUF becomes even more secure," says Lee.

The researchers wanted to achieve this by developing a matching pair of PUFs on two chips. One could authenticate the other directly without the need to store PUF data on third-party servers.

As an analogy, imagine a sheet of paper that has been torn in half. The torn edges are random and unique, but the pieces have a common randomness because they fit together perfectly along the torn edge.

While CMOS chips cannot be torn in half like paper, many are fabricated simultaneously on a silicon wafer that is disassembled into individual chips. By incorporating a common randomness at the edge of two chips before they are disassembled, the researchers were able to create a double PUF that is unique to these two chips. "We needed to find a way to do this before the chip leaves the factory to provide additional security. Once the finished chip enters the supply chain, we no longer know what could happen to it," explains Lee.

Share Randomness

To create the twin PUF, the researchers alter the properties of a series of transistors fabricated along the edge of two chips using a process called gate oxide breakdown. Essentially, they pump high voltage into a pair of transistors by illuminating it with an inexpensive LED until the first transistor breaks through. Due to tiny manufacturing tolerances, each transistor has a slightly different breakdown time. The researchers can use this unique breakdown state as the basis for a PUF.

To enable a double PUF, the MIT researchers fabricate two pairs of transistors along the edge of two chips before they are split. By connecting the transistors with metal layers, they create paired structures that have correlated breakdown states. In this way, they enable each pair of transistors to share a unique PUF.

After using LED light to create the PUF, they cut the chips between the transistors so that there is a pair on each device. This gives each individual chip a common PUF. "In our case, the transistor failure was not modeled well in many of our simulations, so there was a lot of uncertainty about how the process would play out. The novelty of this work is to identify all the steps and their sequence required to generate this common randomness," says Lee.

After fine-tuning their PUF generation process, the researchers developed a prototype of a pair of twin PUF chips where the randomization matched with a reliability of more than 98 percent. This would ensure that the generated PUF key would consistently match and enable secure authentication. Because they created this twin PUF using circuit techniques and low-cost LEDs, the process would be easier to implement at scale than other methods that are more complicated or incompatible with standard CMOS fabrication.

"In the current design, the shared randomness generated by transistor failures is immediately converted into digital data. Future versions could preserve this shared randomness directly in the transistors, strengthening security at the most basic physical level of the chip," says Lee. "There is a rapidly growing demand for physical security for edge devices, for example between medical sensors and devices on the body, which often operate under strict power constraints. A twin-paired PUF approach enables secure communication between nodes without high protocol overhead, providing both energy efficiency and high security. This first demonstration paves the way for innovative advances in secure hardware design," adds Chandrakasan.

The research is funded by Lockheed Martin, the MIT School of Engineering MathWorks grant and the Korea Foundation for Advanced Studies grant. (sg)

Original article on MIT News from February 20, 2026.