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Researchers at MIT have developed a scalable and cost-effective approach to seamlessly integrate high-speed gallium nitride transistors into a standard silicon chip.

The ongoing AI boom has led to a rapidly increasing demand for chips that require high performance as well as high energy efficiency. The semiconductor material gallium nitride is considered one of the possible keys for the next generation of high-speed communication systems and the power electronics needed for modern data centers. Unfortunately, the high costs of gallium nitride (GaN) and the specialization required to incorporate this semiconductor material into conventional electronics have limited its use in commercial applications.

Researchers from MIT and other partner institutes have now presented a manufacturing process that promises to integrate high-performance GaN transistors cost-effectively and scalably into standard silicon CMOS chips. The technology is also compatible with existing semiconductor foundries, thereby avoiding the need for costly new manufacturing facilities with new machinery.

Subsequent bonding of GaN transistors onto the silicon chip

The method involves constructing many tiny transistors on the surface of a GaN chip and cutting out each individual transistor. Then, only the required number of transistors are integrated onto a silicon chip. This is done in a low-temperature process that preserves the functionality of both materials.

According to the researchers, the resulting costs remain minimal, as only a tiny amount of GaN material is added to the chip. Nevertheless, the resulting product receives a significant performance boost through the compact high-speed transistors integrated in this way. By splitting the GaN circuit into discrete transistors that can be distributed over the silicon chip, the technology is also able to lower the temperature of the overall system.

The researchers demonstrated the process by producing a power amplifier that achieves higher signal strength and greater efficiency than devices with silicon transistors. In a smartphone, this could improve call quality, increase wireless bandwidth, enhance connectivity, and extend battery life. The result was presented in the study "3D-Millimeterwave Integrated Circuit (3D-mmWIC): A Gold-Free 3D-Integration Platform for Scaled RF GaN-on-Si Dielets with Intel 16 Si CMOS" at the IEEE Radio Frequency Integrated Circuits Symposium (June 15-17) in San Francisco.

Since their method fits into standard procedures, it could improve both current and future technologies. The researchers believe that the new integration scheme could even enable quantum applications, as GaN performs better than silicon at the cryogenic temperatures required for many types of quantum computers.

"If we manage to reduce costs, improve scalability, and simultaneously increase the performance of the electronic device, then it is a no-brainer to use this technology. We have combined the best of silicon with the best possible gallium nitride electronics. These hybrid chips can revolutionize many commercial markets," says Pradyot Yadav, an MIT graduate student and the lead author of the research paper on the method presented.

Replacement of transistors

After silicon, gallium nitride is the second most widely used semiconductor in the world. Due to its unique properties, GaN chips are currently primarily used in applications such as lighting, radar systems, and power electronics. To fully exploit the performance of semiconductors based on this material, it is important that GaN chips are connected to digital chips made of silicon, also known as CMOS chips. To enable this, some integration methods involve soldering GaN transistors onto a CMOS chip, which, however, limits the size of the GaN transistors. The smaller the transistors are, the higher the frequency at which they can operate.

Conventional methods typically involve integrating an entire gallium nitride wafer onto a silicon wafer. This is labor-intensive and expensive because silicon as a raw material is significantly cheaper. Additionally, the required gallium nitride material is usually needed only in a few tiny transistors. As a result, the rest of the material on the GaN wafer is generally wasted.

"We wanted to combine the functionality of GaN with the performance of digital silicon chips without compromising on cost or bandwidth. We achieved this by placing super tiny discrete gallium nitride transistors directly on the silicon chip," explains Yadav.

The new chips are the result of a multi-step process. First, a densely packed array of tiny transistors is fabricated across the entire surface of a GaN wafer. Using very fine laser technology, each one is cut to the transistor size of 240 by 410 microns, creating what is known as a dielet.

Each transistor is equipped with tiny copper pillars, which are directly connected to the copper pillars on the surface of a standard silicon CMOS chip. The copper-to-copper connection can be made at temperatures below 400 degrees Celsius, which is low enough not to damage either material.

Current GaN integration techniques require connections with gold, an expensive material that needs much higher temperatures and stronger bonding forces than copper. Since gold can contaminate the tools used in most semiconductor foundries, special facilities are generally required. "We wanted a process that is cost-effective, requires low temperatures and low forces, and copper is better than gold in all these aspects. At the same time, it has better conductivity," says Yadav.

New tools are used

To enable the integration process, a new specialized tool was developed, which can carefully integrate the extremely tiny GaN transistor into the silicon chips. The tool uses a vacuum to hold the dielet while moving onto a silicon chip and adjusts the copper connection interface with nanometer precision.

Using advanced microscopy, the interface is monitored, and when the dielet is in the correct position, the GaN transistor is bonded to the chip using heat and pressure. "For each process step, I had to find a new person who mastered the technique I needed, learn from them, and then integrate it into my platform. It was two years of constant learning," says Yadav.

After perfecting the manufacturing process, the researchers demonstrated it by developing power amplifiers, i.e., high-frequency circuits that amplify wireless signals. According to the study, the resulting semiconductor products achieved higher bandwidth and better amplification than comparable chips made with conventional silicon transistors. Each compact semiconductor has an area of less than half a square millimeter.

Since the silicon chip used for the demonstration is based on state-of-the-art Intel 16 22nm FinFET metallization and passivation options, they were also able to include components commonly used in silicon circuits, such as neutralization capacitors. This significantly improved the amplifier's gain, bringing it one step closer to the next generation of wireless technologies.

"To counteract the slowing down of Moore's Law in transistor scaling, heterogeneous integration has proven to be a promising solution for further system scaling, reducing the form factor, improving performance efficiency, and optimizing costs. Particularly in wireless technology, the close integration of compound semiconductors with silicon-based wafers is crucial for the realization of unified systems from integrated front-end circuits, baseband processors, accelerators, and memory for next-generation antenna-to-AI platforms. This work represents a significant advancement by demonstrating the 3D integration of multiple GaN chips with silicon CMOS and pushing the boundaries of current technological capabilities," says Atom Watanabe, a researcher at IBM who was not involved in this work. (sg)

*Original publication on MIT News from 18.6.2025