CMOS 2.0 European University Consortium for Advanced Manufacturing Technologies

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Imec has launched a consortium with 26 European university groups that will work together on the technology roadmap beyond CMOS scaling (CMOS 2.0). This initiative will focus on design automation and chip architecture research for the next generation of chips.

Imec has set up a European university consortium under the motto CMOS 2.0. In it, 26 university groups are working on technologies for future chips that go beyond the classic scaling of transistors in order to develop the manufacturing technologies of the future. The focus is on design automation and chip architectures for future system generations. The consortium will benefit from the NanoIC pilot line, which translates academic findings into industry-oriented innovations.

CMOS 2.0 describes an approach in which progress is no longer to be achieved solely through smaller transistor structures. The focus is on 3D wafer stacking and heterogeneous integration. The aim is to enable computing systems with higher energy efficiency and performance and to combine different functions in several stacked layers.

Pooling Expertise, Making Progress

"The appeal of the CMOS2.0 concept is obvious, but so are the obstacles," says Sahar Sahhaf, Director of Academic Partnership Development. "Taking advantage of both connectivity and heterogeneous integration enabled by 3D wafer stacking will reshape every phase of the design and chip architecture. This will require the pooling of expertise, close collaboration and coordination."

"This university research consortium aims to integrate CMOS 2.0 technology into the entire design stack, from electronic design automation (EDA) to system architecture," adds Technical Director Mehdi Tahoori. "It aims to stimulate the broader research and scientific community on various aspects of the CMOS 2.0 revolution. Imec plays a unique and critical role in connecting academic research with industry needs and expanding the roadmap of technology scaling with CMOS 2.0."

According to Imec, the consortium is also intended to strengthen the exchange between universities and industry. Funding is planned for 26 doctoral students who will remain at their respective universities and be integrated into the existing research groups there. They will also have access to Imec's NanoIC pilot line in Leuven.

The pilot line is intended to provide early access to process design kits for advanced logic, memory and 3D technologies. The aim is for doctoral students to gain experience with system-related issues at an early stage of their research. Imec sees this as a contribution to technology transfer between academic research and industrial development as well as to the development of skilled workers in the European semiconductor sector.

The following universities and institutions are involved in the CMOS 2.0 consortium:

• National Technical University of Athens
• Delft University of Technology
• École Polytechnique Fédérale de Lausanne (EPFL)
• Swiss Federal Institute of Technology Zurich
• Karlsruhe Institute of Technology
• Katholieke Universiteit Leuven
• KTH Royal Institute of Technology
• LIRMM, University of Montpellier, CNRS
• Politecnico di Torino
• Sabancı University
• Complutense University of Madrid
• University of Ghent
• Université libre de Bruxelles
• University of Thessaly

(sg)

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