Clock generators Low-jitter oscillators for high clock performance

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Clock oscillators provide the heartbeat, or timing of modern circuits, by clocking the system components. As system speeds increase to hundreds of MHz and more, these clocks must be faster and exhibit very low jitter, typically less than 100 fs, to maintain system performance. Moreover, they must maintain their low jitter over a prolonged period, despite temperature and voltage fluctuations.

Rolf Horn is Application Engineer at DigiKey.

A certain amount of jitter is caused by noise and distortions on the signal path and can be somewhat reduced by reclocking and retiming techniques. However, jitter is also generated by the clock source, which is usually an oscillator. This is due to various physical phenomena, e.g., thermal noise, process flaws, power supply noise, other external disturbances entering the clock oscillator, material tensions, and many other subtle factors. Regardless of the source, everything must be done to minimize the inherent clock jitter, as the defects are irreversible.

This article discusses jitter problems from different perspectives. Subsequently, various clock oscillators from Abracon LLC are introduced and it is shown how jitter can be minimized by adapting the performance of the clock oscillator to the application.

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Gallery with 5 images

Basics of Jitter

Clock jitter refers to the deviation of a clock edge from its ideal position in time. This jitter impairs the temporal precision and accuracy of the transmission of data signals clocked by the clock signal, leading to a deterioration of the signal-to-noise ratio (SNR) in the receiver decoding/demodulation circuits or other system ICs. This results in a higher bit error rate (BER), increased retransmissions, and a lower effective data throughput.

Due to its criticality, clock jitter in systems that transmit a signal from a sending source across cables, connectors, or PCBs to a receiver is often analyzed. Depending on the application, it can be characterized in many ways, including cycle-to-cycle jitter, period jitter, and long-term jitter (Figure 1).

• Cycle-to-cycle jitter refers to the change in the clock period over two consecutive cycles and has nothing to do with the change in temporal frequency.

• Period jitter is the deviation of any clock period from its average period. It is the difference between the ideal and the actual clock period and can be specified either as RMS period jitter (Root-Mean-Square) or as peak-to-peak period jitter.

• Long-term jitter is the deviation of the clock edge from its ideal position over a longer period of time. It is somewhat comparable to drift.

Jitter can disrupt the timing of other sub-functions, components, or systems used for low BER data recovery, or components such as memory elements or processors in a synchronous system. In the eye diagram of Figure 2, this is seen as a widening of the crossover point in the bit clock.

In serial data connections, the circuit on the receiver side must try to restore its own clock for optimal decoding of the data stream. To do this, it must synchronize with the source clock, which often happens with a phase-locked loop (PLL). Jitter impairs the system's ability to do this precisely and jeopardizes the ability to recover the data with a low BER.

Note that jitter can be measured both in the time domain and in the frequency domain; both views are equally valid for the same phenomenon. Phase noise is a view of the noise spectrum around the oscillator signal in the frequency domain, while jitter is a measure of the temporal precision of the oscillator period in the time domain.

Jitter measurements can be expressed in various ways. Common units are time such as "jitter of 10 ps". The root mean square (RMS) of phase jitter is a time domain parameter that is derived from the measurement of phase noise (frequency domain). Jitter is sometimes also referred to as phase jitter, which can be confusing, but it is still the Jitter parameter in the time domain.

When the operating frequencies of the connections and their clocks rise from a few tens of MHz to hundreds of MHz and more, the allowable jitter of the clock source drops to about 100 fs or less. These frequencies are for optical modules, cloud computing, networks, and high-speed Ethernet, all functions and applications that require a carrier frequency between 100 and 212/215 MHz and data rates of up to 400 Gbit/s.

The use of the quartz

The most common method of producing a stable, consistent, and frequency-accurate clock signal is through the use of a quartz oscillator. An associated oscillator circuit supports the quartz. There are many such circuit families, each with different trade-offs. Crystals have been used since the 1930s for medium frequency (300 kHz to 3 MHz) and high frequency (3 to 30 MHz) wireless radio communication.

A widely used approach to generating low jitter clock signals is to use one of the many variants of PLL-based architectures. For example, the AX5 and AX7 ClearClock family components from Abracon, which have a 5mm x 3.2mm and 5mm x 7mm casing respectively, use advanced PLL technology for a superbly low jitter performance (Picture 3).

In addition to the operating frequency and the oscillator design, the jitter performance is also influenced by the physical size of the quartz in the oscillator core. The smaller this crystal is, the more difficult it becomes to achieve excellent RMS jitter performance.

For clock solutions in the 100 to 200 MHz range and in smaller form factors than the PLL-based AX5 and AX7 devices, a new oscillator architecture is required. These requirements for a smaller size are typically associated with the latest generation of optical transceivers and modules. There are four proven ways to develop a clock oscillator in the 100 to 200 MHz range:

• Using a quartz oscillator with an inverted mesa quartz as a resonator element.

• Using a quartz oscillator with a third harmonic overtone (third harmonic) quartz blank as a resonator element.

• Using an oscillator loop that is based on a third harmonic overtone / fundamental under 50 MHz quartz blank or a temperature compensated quartz oscillator under 50 MHz combined with a PLL IC with integral or fractional mode.

• Using a MEMS (MicroElectroMechanical System) oscillator loop under 50 MHz combined with a PLL IC with integral or fractional mode.

Option 1 neither offers the best RMS jitter performance nor is it the most cost-effective solution. Option 3 is complicated and has performance deficiencies, while the MEMS resonator approach of option 4 does not meet the primary performance criteria of 200 fs RMS jitter maximum. In contrast, Option 2 uses an optimally designed quartz blank with third harmonic, taking into account electrode geometry and optimizing the cut angle. This combination is optimal in terms of cost, performance, and size.

With this approach, Abracon has developed "third harmonic" ClearClock solutions (Image 4). These components use a quieter architecture to provide superior, extremely low RMS jitter performance and extreme energy efficiency in miniature housings of just 2.5 mm x 2.0 mm x 1.0 mm.

In this scheme, a careful design of the third harmonic quartz combined with the right filtering and the "trapping" of the desired carrier signal provides excellent RMS jitter performance at the desired carrier frequencies.

In this architecture, no typical PLL approach is used, so there is no up-conversion. Consequently, no fractional or integer PLL standard multiplication is required, and the final output frequency is in a one-to-one correlation with the third harmonic quartz resonance frequency. The omission of fractional or integer multiplication simplifies the design and allows for minimal jitter at the smallest possible size.

Specifications and Performance in Reality

Clock oscillators are more than just a quartz and its analog circuit. They incorporate buffering to ensure that the oscillator's output load and its short and long-term fluctuations don't impact the device's performance. They also support various digital logic output levels for circuit compatibility. This compatibility eliminates the need for an external logic level converter IC. Such an IC would increase cost, space requirements, and jitter.

Since clock oscillators are used in so many different applications with different rail voltages, they must be offered with a variety of supply voltages such as +1.8, +2.5 or +3.3 V as well as with custom values that typically range from 2.25 to 3.63 V. Moreover, they must be available with different output formats such as LVPECL (Low-Voltage Positive/Pseudo-Emitter-Coupled Logic) and LVDS (Low-Voltage Differential Signaling) among other formats.

A look at two families of quartz clock oscillators, the AK2A and AK3A, shows what can be achieved through a sophisticated understanding and integration of materials, design, architecture, and test. The two families are similar, with the main differences being in size and maximum frequency.

The AK2A family: This family of quartz oscillators is offered with nominal frequencies from 100 to 200 MHz and is available with operating voltages of 2.5, 3.3 and 2.25 to 3.63 V with LVPECL, LVDS and HCSL differential output logic.

All family members have similar performance, including low RMS jitter. The AK2ADDF1-100.000T, for example, is a 100.00 MHz, 3.3 V device, with LVDS outputs and an RMS jitter of 160.2 fs (Figure 5). Its frequency stability is excellent at more than ±15 ppm over temperature, and it is supplied in a 6-pin SMD (surface mount) package measuring 2.5 mm x 2.0 mm x 1.0 mm.

With increasing clock frequency, however, the jitter must decrease in order to maintain system-level performance. With the AK2ADDF1-156.2500T, a 156.25 MHz LVDS oscillator, the typical RMS jitter drops to 83 fs.

The AK3A family: The components of the AK3A family are slightly larger than those of the AK2A family with a footprint of 3.2 mm × 2.5 mm × 1.0 mm (Image 6). Versions are available that are specified up to 212.5 MHz, so slightly higher than the 200 MHz limit for the AK2A family.

The general specifications for this AK3A component are similar to those of the corresponding member of the AK2A family. An example is the AK3ADDF1-156.2500T3, a 156.25 MHz LVDS oscillator, which has a typical RMS jitter of 81 fs, thus being slightly better than the corresponding member of the AK2A family.

The jitter for both families varies depending on operating frequency, operating voltage, package size, and choice of outputs.

Additional practical considerations

Having a clock oscillator that only meets specifications on the day it leaves the factory is not enough. As with all components, particularly analog and passive ones, these oscillators experience drift over time due to aging of the materials used and internal stresses.

This fact presents a particular challenge for high-performance clock oscillators, as there are no convenient or simple ways to correct or compensate for this drift by adding software or clever circuits. There are, however, a few ways to mitigate the effects of drift. These include longer burn-in periods by the end user for accelerated aging of the oscillator, or the use of a temperature-stabilized oscillator in an oven-controlled enclosure. The former is time-consuming and challenges the supply chain, and the latter is large, expensive, and energy-hungry.

Recognizing that aging is a critical parameter, Abracon's ClearClock family offers a stringent, comprehensive frequency accuracy over the entire lifespan of the end-product from 10 to 20 years. Abracon guarantees that a frequency stability of better than ±50 ppm will be maintained over this period. This is achieved through the careful selection and fabrication of the third harmonic quartz and its conditioning to achieve a stability of ±15 ppm over -20 to 70 °C, and ±25 ppm over -40 to 85 °C.

As always, engineering is about compromise. Compared to their predecessor models (Gen I AK2 or AX3), the Abracon AK2A and AK3A series offer improved jitter noise performance by using a next generation oscillator ASIC (Gen II), thus ensuring extremely low RMS jitter performance.

This improvement is achieved at the expense of a slight increase in power consumption. The maximum power consumption increases from 50 mA with Gen I to 60 mA with Gen II, with the low voltage components consuming about half of this value. Therefore, the second generation ClearClock oscillators offer extremely low RMS jitter at the same time as low power consumption.

Conclusion

Clock oscillators are the heartbeat of a data link or clock function, and their accuracy, jitter, and stability are critical parameters in achieving the required system-level performance, including a high SNR and low BER. Higher clock frequencies can be achieved through innovative material selection and architectures that adhere to the stringent performance requirements of the industry and its various standards. Abracon's AK2A and AK3A series stand out with jitter under 100 fs in the 100 to 200 MHz range in SMD packages that measure just a few millimeters on each side. (tk)