Chip Design Analysis of Signal Integrity And Power Integrity in 3D IC Design

The semiconductor industry is pushing the boundaries of traditional scaling approaches. That's why 3D IC technology has emerged as a critical path for continued innovation. A key aspect of this revolution is the analysis of signal integrity and power integrity (SI/PI).

The relentless pursuit of higher performance and greater functionality has led the semiconductor industry through several phases of transformation. The most recent shift is from traditional monolithic SoCs to heterogeneous integrated advanced package ICs, including three-dimensional integrated circuits (3D ICs). The new technology is helping semiconductor companies to uphold Moore's Law.

However, these advances bring with them increasingly complex challenges, particularly in terms of power integrity (PI) and signal integrity (SI). Once secondary, SI/PI have become critical disciplines in modern semiconductor development. As data rates increase to several gigabits per second and power supply requirements become more stringent, error margins are decreasing dramatically, making SI/PI expertise essential. The fundamental challenge is to ensure clean and reliable signal transmission and stable power supply across complex systems.

In the following, the specific SI/PI challenges in 3D IC designs compared to conventional SoCs are explained. It then develops an advanced verification strategy to address these complexities, analyzes the roles and interdependencies of players in the 3D IC ecosystem, and illustrates these concepts with a real-world success story. It concludes by discussing how these innovations are advancing the future of semiconductor design.

Conventional SI/PI Vs. 3D IC Approaches

For conventional SoC components destined for a PCB system, SI and PI analysis typically validates individual components prior to system integration. SoCs, packages and PCBs are often treated as separate entities, allowing for sequential analysis and optimization. For example, component-level power demand analysis can be performed on the monolithic SoC and its package, while signal integrity analysis validates individual channels. The design process is often split between separate packaging and PCB teams working in parallel. These teams must eventually cooperate to overcome design trade-offs. An example of this is the allocation of timing or voltage margins between the package and the PCB to accommodate routing constraints. Although this compartmentalized approach is effective for traditional designs, it is inadequate for the inherent complexities of 3D ICs.

The architecture of a 3D IC is not just a collection of components, but a highly dense system of mini-subsystems characterized by the vertical stacking of multiple dies. Interfaces between the dies, silicon vias (TSVs) and microbumps create a dense, highly interactive electrical environment. In this environment, power and signal integrity issues are tightly interwoven and can propagate through multiple layers. The tight integration and proximity of these leads to new coupling mechanisms and power challenges that can be ineffectively addressed by sequential, isolated analysis. In contrast to a conventional process, 3D ICs therefore require holistic, parallel validation from the outset, with SI and PI analyses starting early and involving all components simultaneously.

Progressive Verification

To navigate the complex landscape of 3D IC design, a progressive verification strategy is crucial. This principle recognizes that design information is sparse in the early stages and becomes more detailed over time. The core idea behind progressive verification is to initiate the analysis as early as possible with available inputs, get the design on the right track and turn the final verification step into a confirmation instead of discovering fundamental problems. Depending on the availability of details, different analysis requirements are considered, starting with minimal inputs and progressively incorporating more specific data.

The various analyses and their timing in the design flow are summarized below:

• Early architectural feasibility and pre-layout analysis: In the initial planning phase, before detailed layout information is available, the focus is on architectural feasibility studies. This includes estimating electricity budgets and defining higher-level interfaces. Early analysis can begin even with rough inputs. For example, signal integrity analysis prior to layout can model representative interconnect structures, such as an interposer bridge. By defining a "framework" for achievable performance based on preliminary values, designers can set realistic expectations and guidelines for subsequent layout phases. This proactive approach helps to identify potential bottlenecks and ensures a robust electrical foundation.
• Layout planning and implementation analysis: When the development process moves on to layout planning and initial implementation, the guidelines from the early analysis are translated into a physical layout. At this point, more in-depth analysis becomes possible. This includes a detailed analysis of the Power Delivery Network (PDN) to verify power distribution to the stacked dies and substrate. Verification of the signal path with actual component connections can also begin, enabling early identification and optimization of critical signal paths. This iterative layout and analysis process allows for continuous refinement and ensures that the physical implementation matches the electrical performance targets.
• Detailed electrical analysis with vendor-specific IP model: The final phase of advanced verification involves comprehensive electrical analysis using actual, vendor-specific intellectual property (IP) models. Given the fledgling stage of 3D IC die-to-die standards (e.g. UCIe, BoW, AIB), which are less mature than established protocols such as DDR or PCIe, this detailed analysis is all the more important. Developers perform thorough S-parameter modeling of impedance networks and feed these models with accurate performance values provided by die developers and other stakeholders. This detailed analysis provides a comprehensive view of the electrical performance of the design and ensures that all critical signal paths and power delivery mechanisms meet specifications under real-world operating conditions.

The 3D IC Ecosystem

The complexity of 3D IC designs requires a highly collaborative environment involving different stakeholders, each with unique perspectives and challenges. Effective communication and early engagement between these teams is critical to successful integration.

System architects are responsible for the overall layout planning and for determining the number of chiplets, the baseband dies and the required communication channels between them. Their challenge is to optimize the overall system architecture in terms of performance, energy consumption and space requirements, taking into account the physical constraints imposed by 3D integration.

Developers focus on individual die architectures and monitor I/O planning and internal power distribution. They must accurately communicate their power requirements and I/O characteristics to ensure compatibility within the stacked system. Their main challenge is to optimize die-level performance while meeting system-level constraints and ensuring robust power supply and signal transmission for all interfaces.

Layout teams are responsible for the physical implementation, which includes the layout at die level, the substrate layout and all silicon connections (e.g. interposers and bridges). Often different layout teams take care of different aspects of the realization, which requires careful coordination. Their challenges include managing extreme density, minimizing parasitic effects and ensuring manufacturability across multiple layers.

SI/PI and Verification teams act as technical advisors, providing guidance and feedback at every level. They advise system architects on bump-out strategies for die layouts and work with die developers to optimize the performance and number of mass bumps. Your role will be to proactively identify and resolve potential SI/PI issues throughout the design cycle to ensure electrical performance targets are met.

Mechanical and thermal teams ensure structural integrity and control heat dissipation. Both are critical to the long-term reliability and performance of designs, as 3D ICs present significant mechanical and thermal challenges beyond electrical aspects. For example, the close proximity of dies can lead to localized hotspots and mechanical stresses due to different thermal expansion coefficients.

By using a progressive verification methodology, these different stakeholders can communicate early and continuously, creating a collaborative environment that makes it much easier to develop a functional and reliable 3D IC design.

Chipletz' Proof of Concept

The effectiveness of a progressive verification strategy and collaborative ecosystem is best illustrated by real-world applications. Chipletz, a pioneering start-up in the field of substrate manufacturing, illustrates successful navigation through complex 3D IC designs through a strategic partnership with an EDA provider. Chipletz selected Siemens as a strategic EDA provider for its smart substrate products and specifically sought tools that could support advanced 3D IC design requirements.

At the time, many industry-standard EDA tools were primarily tailored to traditional package and PCB architectures. Chipletz presented Siemens with an enormous challenge: the designs involved huge layouts with up to 50 million pins, requiring sophisticated analysis tools with unprecedented capacity and layout tools capable of handling such complicated structures.

To improve the capacity and capabilities of the tools, Siemens utilized its research and development teams. The collaboration demonstrated not only that Siemens is capable of handling these complex architectures, but also that the company can perform meaningful electrical analysis on such large designs. The initial efforts focused on fundamental aspects such as analyzing the DC IR drop across the substrate and early PDN analysis.

Through these fundamental steps, Siemens has demonstrated the power of its tools and, most importantly, its commitment to working with Chipletz to overcome difficult hurdles. The partnership enabled Chipletz to successfully complete their first visualization model. The company is now working on the second revision of its design. This success underscores the importance of flexible EDA tools and close collaboration between vendors and customers when it comes to pushing the existing boundaries of 3D IC innovation.

Incentive for innovation

3D ICs are undoubtedly here to stay. Major semiconductor companies are increasingly integrating various forms of 3D packaging into their product roadmaps. This shift represents a fundamental change in the approach to system design and integration. As the industry continues to view 3D IC integration as a critical enabler for next-generation systems, the methodologies and collaborative approaches for SI and PI described in this article will become increasingly important.

The progressive verification strategy combined with close collaboration between various stakeholders provides a robust framework to address the complex challenges of 3D IC design. Companies and individuals who master these techniques will be uniquely positioned to lead the next wave of semiconductor innovation and develop the high-performance, energy-efficient systems that will power our increasingly digital world. With its comprehensive portfolio and collaborative partnerships such as with Chipletz, Siemens is actively helping customers lead the way in successful 3D IC designs. (sb)

Todd Burkholder is a Senior Editor at Siemens DISW. For more than 25 years, he has worked as an editor, writer and ghostwriter with internal and external clients to create print and digital content for a wide variety of EDA technologies. He began his career in marketing for high technology and other industries in 1992 after earning a Bachelor of Science degree from Portland State University and a Master of Arts degree from the University of Arizona.

John Caka is a senior SI/PI engineer at Siemens EDA. During his time at Siemens, where he has held various positions, he has developed a unique perspective on the challenges facing today's designers in high-speed electronics design, signal integrity and power integrity engineering. His combination of hands-on design experience and customer-centric expertise makes him uniquely qualified to discuss the evolving landscape of SI/PI analysis in advanced packaging technologies such as 3D IC.

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