Semiconductor manufacturing with AI and ML From chiplets to edge computing: How a test industry is changing

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Wuxi InfiMotion Technology Co., Ltd.

Artificial Intelligence and Machine Learning improve the quality and efficiency in semiconductor manufacturing. Test processes can be optimized and machine learning methods detect patterns and anomalies that humans do not discover.

Ira Leventhal is Vice President, Applied Research & Technology, Advantest America INC.

Dr. Matthias Sauer is Lab Lead Boeblingen & China, Director Applied Research & Venture Team, Advantest Europe GmbH.

In the semiconductor industry, AI and machine learning (ML) are at the forefront of development, as new manufacturing processes and ever-increasing integration density pose great challenges to semiconductor testing. The semiconductor testing industry is well-positioned by using AI and ML to analyze and correlate data along the entire semiconductor value chain. Thus, AI and ML can fundamentally change the semiconductor industry. The quality and efficiency in semiconductor testing increase. This is made possible by a new generation of AI processors.

However, these AI processors, often developed by new market participants such as hyperscalers and start-ups, are not entirely unproblematic. These include the miniaturization of process nodes, the more complex integration of heterogeneous units, improved communication architectures, and the increased power consumption and resulting heat generation. Industry initiatives include adaptive real-time testing, predictive maintenance, improvements in DC testing, in-situ thermal testing and optimization, and efficient workflows.

New possibilities with the AI components

In the pre-chiplet era, traditional CPUs were targeted at specific applications. In contrast, the new chiplet-based AI building blocks allow flexibility for applications that were not known at the time of their development. The test strategies for these building blocks must generate enough data to be able to assign them to new applications after the tests are completed. In the traditional test world, the device under test (DUT) consists of a housing with one or a few components, and the tester must have direct access to most of the DUT's connections (pins). Each test step, from post-silicon validation to system-level testing, has a clearly defined purpose and collects test data.

With the transition to chiplet-based modules that enable integration of CPU, GPU, memory and other functions in a single 2.5D or 3D casing, the requirements for testing procedures change. Here, the tester can only access a limited number of pins. Therefore, the tester must be able to extract and use valuable data at each test step to optimize both the current test step and other design, manufacturing, and test steps.

With limited pin access, the tester must deduce the actions at unobservable nodes. A central aspect is maximizing the benefit from directly captured data in all manufacturing and test steps, including data from on-chip sensors.

Effective predictive and adaptive testing approaches

In the chiplet world, testers always have to be one step ahead of the system. Smart Pairing, a form of application-based real-time binning, takes into account factors such as voltage, speed, and power consumption to ensure that all chips in a package have compatible electrical and thermal properties. This minimizes differences in reliability, signal delay and power imbalance. Rule-based decision models that worked in the pre-chiplet world still serve certain purposes.

In the chiplet era, however, the ML model is also crucial to meet complex real-time decision requirements. To be able to recognize subtle fault mechanisms, a wide range of input data is necessary. In addition, with limited test access in the final housing, on-chip sensor data, device settings, sensor data as well as upstream data from development and manufacturing are becoming increasingly important. ML can use all these data to enable effective predictive and adaptive test approaches.

How a pre-existing ML model helps with packaging

The aim is to detect errors as early as possible in the test chain before the wafers are assembled into packaged components. In the chiplet/HI world, the cost and complexity of packaging increase. For this reason, only 'known-good die' (KGD) should be installed in a housing. An upstream ML model allows real-time decisions about KGDs based on data from several test steps. Previous research has shown that such methods can significantly reduce test costs.

However, there are exceptions: For example, it can be advantageous to move a long test from packaging test to system test (SLT) where the test time is less costly. An ML strategy can help optimize the entire test process. Throughout the entire test process, it is important to use AI and ML to test AI devices, analyze test data, correlate data across multiple wafers, and accurately track each chip's path through the assembly process.

Various tools and algorithms, applied to design, manufacturing, test, and device data, enable correlation across the entire manufacturing process and provide insights that allow for process optimization.

Automatic corrective actions during production.

Increasing test requirements are boosting the need for AI and ML-supported prediction methods. The real-time execution of test code allows for automatic corrective measures during production to keep costs under control. One test customer has found that ML-based parametric predictions can reduce the parametric test time by 50 percent or more while successfully identifying performance-adjusted components without compromising quality.

To protect sensitive intellectual property in outsourced production environments, modern data security techniques are essential. The semiconductor supply chain often includes contract manufacturing and testing services. The test devices in a facility can process parts from multiple IC suppliers. In this case, it is not trivial for the suppliers to protect all aspects of the sensitive test IP. A facility is expected to protect its environment, but in complex supply chains, it can be difficult to delineate the environment.

AI/ML in test environments with Edge Computing.

One approach is the zero-trust security model. It means that products and services cannot trust other products and services by default. A zero-trust inference environment in conjunction with a test system protects against threats both inside and outside traditional network boundaries by reducing the 'trust zone' from the network level to individual nodes or applications. Interactions between trust zones require continuous authentication.

Edge computing is proposed as an effective solution for real-time ML decision-making in the test environment as it offers low latency, improved bandwidth efficiency, scalability, as well as enhanced security and data protection. It enables dynamically adaptive test sequences, which minimize the cost of testing (COT) and maximize yield.

Edge applications for semiconductor manufacturing with AI/ML.

Advantest has introduced ACS RTDI. This is a platform that collects, analyzes, stores, and monitors semiconductor test data. It uses edge computing and low-latency analytics in a zero-trust environment to streamline data usage and improve quality, yield, and operational efficiency.

The ACS Edge-HPC server works in conjunction with Advantest's V93000 and other ATE systems to handle compute-intensive workloads. The V93000 system is flexible in testing different types of ICs and supports instrument cards for various test requirements. Lowering test costs through ML techniques has already been explored by Advantest and its customers, with significant financial benefits observed. Future work aims to develop advanced models that accurately predict yield, quality, and reliability. Advantest also uses AI and ML in products like ACS Adaptive Probe Cleaning and ACS EASY to enhance the testing of AI-enabled chips and analyze yield issues.

In summary, the use of AI, ML, and Edge Computing will significantly shape semiconductor manufacturing, especially for chiplets and HI in 2.5D/3D packages. Both techniques enable a comprehensive analysis and appropriate response to test data, leading to increased efficiency in the semiconductor industry. (heh)

Link: ACS Real-Time Data Infrastructure from Advantest. (external link).