Research 3D chips in high-rise architecture: MIT pushes the boundaries of semiconductor manufacturing

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At MIT, a research team has designed an intriguing stacking method that could exponentially increase the number of transistors on chips. Based on this method, more efficient AI hardware could be developed, among other things.

A team from the Massachusetts Institute of Technology (MIT) has developed a process that allows high-quality semiconductor layers to grow directly on top of each other without relying on silicon substrates. This enables a significantly higher density of transistors, faster communication between layers, and consequently more efficient use of available space. Thanks to low manufacturing temperatures (+380 °C), the underlying electronics remain intact, which previously posed a technical challenge.

Stack instead of scatter

As the electronics industry has been approaching the limit of transistors that can be accommodated on a single layer of a computer chip for years, chip manufacturers are attempting to increase the number of transistors vertically instead of spreading them out over a surface. Accordingly, there is an effort to stack multiple layers with transistors and semiconductor elements on top of each other—like converting a row of townhouses into a skyscraper. Such multilayer chips could process exponentially more data and perform much more complex functions than today's electronics.

However, a major hurdle is the platform on which the chips are built. Today, silicon wafers serve as the main framework where high-quality, single-crystal semiconductor elements are grown. Each stackable chip must have a thick silicon "base" as part of each layer, which slows down the communication between the functional semiconductor layers.

MIT engineers have introduced a multilayer chip design that does not require silicon wafer substrates and operates at sufficiently low temperatures to preserve the underlying circuits. In the journal Nature, the team reports on the application of the new method to produce a multilayer chip with alternating layers of high-quality semiconductor material grown directly on top of each other. The method allows engineers to fabricate high-performance transistors as well as memory and logic elements on any crystalline surface—not just on the bulky crystal lattice of silicon wafers.

Because the silicon substrates are eliminated, the researchers believe that multiple semiconductor layers can be in more direct contact, leading to better and faster communication and computation between the layers. Such chips could make portable devices as fast and powerful as today's supercomputers, also capable of storing huge amounts of data like physical data centers.

The MIT co-authors of the study include lead author Ki Seok Kim, Seunghwan Seo, Doyoon Lee, Jung-El Ryu, Jekyung Kim, Jun Min Suh, June-chul Shin, Min-Kyu Song, Jin Feng, and Sangho Lee, as well as members from the Samsung Advanced Institute of Technology, Sungkyunkwan University in South Korea, and the University of Texas in Dallas.

Tiny "seed pockets"

In 2023, Kim's group reported on a method they developed to grow high-quality semiconductor materials on amorphous surfaces, similar to the topography of semiconductor circuits on finished chips. The material they grew was a 2D material known as "transition-metal dichalcogenides" (TMD), considered a promising successor to silicon for the production of smaller, high-performance transistors.

TMDs combine extreme thinness with outstanding electronic and optical properties, making them of interest in both fundamental research and high-tech applications. They are considered promising materials to complement or even replace silicon in microelectronics, especially in areas like flexible electronics and miniaturization. Such materials can retain their semiconductor properties even at a size as small as a single atom, whereas silicon's performance significantly diminishes at that scale.

In their previous work, Kim's team grew TMDs on silicon wafers with amorphous coatings as well as on pre-existing TMDs. To ensure the atoms arranged themselves in a single-crystalline form rather than in a polycrystalline disorder, Kim and colleagues covered a silicon wafer with a very thin layer of silicon dioxide, which they patterned with tiny openings or pockets—a mask. They then passed a gas containing atoms over the mask and found that the atoms settled in the pockets as "seeds." The pockets constrained the seeds so they grew in regular, single-crystalline patterns. However, the method previously worked only at about +900 °C.

"You have to grow this single-crystal material at over 400 °C, otherwise the underlying circuit will be completely cooked and ruined," says Kim. "So, our homework was to develop a similar technique at temperatures below 400 °C. If we could achieve that, the impact would be substantial."

Assembly technique

In their new work, the team attempted to refine the method to grow single-crystal 2D materials at sufficiently low temperatures. They found a surprisingly simple solution in metallurgy.

When metallurgists pour molten metal into a mold, nucleation begins, the so-called seeding process. As the molten metal cools, the temperature drops below the melting point, and initial atomic clusters form solid seeds. Metallurgists have found that this nucleation is most likely to occur at the edges of a mold into which liquid metal is poured. "It's known that nucleation at the edges requires less energy—and heat," explains Kim. "We adopted this concept from metallurgy."

The team attempted to grow single-crystalline TMDs on a silicon wafer that already had transistor circuits. First, they covered the circuits with a mask of silicon dioxide, just as in their previous work. They then applied "TMD seeds" to the edges of the individual pockets of the mask and found that these edge seeds grew into single-crystalline material at temperatures of only +380 °C. Seeds that grew further away from the edges of the mask required a higher temperature to form single-crystalline material.

The researchers went a step further and used the new method to produce a multilayer chip with alternating layers of two different TMDs. In this case, it was molybdenum disulfide, a promising material candidate for manufacturing n-type transistors, and tungsten diselenide, a material suitable for making p-type transistors. The team succeeded in growing both materials in single-crystalline form directly on top of each other without the need for an intermediate silicon wafer. According to Kim, this method doubles the density of a chip's semiconductor elements, particularly the metal-oxide-semiconductors (CMOS), which are a fundamental building block of modern logic circuits.

"A product realized with our technique is not just a 3D logic chip but also 3D memory combined," says Kim. "With our growth-based monolithic 3D method, you could grow dozens to hundreds of logic and memory layers directly on top of each other, and they would be able to communicate optimally."

"Conventional 3D chips were manufactured with intermediate silicon wafers by drilling holes into the wafer—a process that limits the number of stacked layers, vertical alignment resolution, and yield," adds lead author Kiseok Kim. "Our growth-based method solves all these problems at once." To commercialize the stackable chip design, Kim founded a company, FS2 (Future Semiconductor 2D Materials). "We have so far demonstrated a concept for small device arrays," he said. "The next step is scaling up to demonstrate the professional operation of AI chips." (sb)

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Link: MIT engineers grow “high-rise” 3D chips