Research 3D chips in building construction: MIT plays with the limits of semiconductor manufacturing

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A team of researchers at MIT has developed an interesting stacking method that could exponentially increase the number of transistors on chips. Among other things, this method could be used to develop more efficient AI hardware.

A team from the Massachusetts Institute of Technology (MIT) has developed a process that allows high-quality semiconductor layers to grow directly on top of each other without having to rely on silicon substrates. This enables a significantly higher density of transistors, faster communication between the layers and consequently a more efficient use of the available space. Thanks to low manufacturing temperatures (+380 °C  / 716°F), the underlying electronics remain intact. This has been a technical challenge until now.

Stacking instead of scattering

Because the electronics industry has been approaching the limit of transistors that can be accommodated on the level of a computer chip for years, chip manufacturers are trying to manufacture the number of transistors in height instead of spreading them out over the surface. Accordingly, there is a drive to stack several areas of transistors and semiconductor elements on top of each other—as if a row of terraced houses were being turned into a skyscraper. Such multi-layered chips could process exponentially more data and perform much more complex functions than today's electronics.

One major hurdle, however, is the platform on which the chips are built. Today, silicon wafers serve as the main framework on which high-quality, single-crystal semiconductor elements are grown. Each stackable chip must have a thick silicon "bottom" as part of each layer, which slows down communication between the functional semiconductor layers.

MIT engineers have unveiled a multilayer chip design that does not require silicon wafer substrates and works at low enough temperatures to preserve the underlying circuitry. In the journal Nature, the team reports on the application of the new method to produce a multilayer chip with alternating layers of high-quality semiconductor material grown directly on top of each other. The method enables engineers to manufacture high-performance transistors as well as memory and logic elements on any crystalline surface—not just on the bulky crystal framework of silicon wafers.

Because the silicon substrates are no longer needed, the researchers believe that several semiconductor layers can be in more direct contact, which in turn leads to better and faster communication and computation between the layers. Such chips could make portable devices as fast and powerful as today's supercomputers, which could also store huge amounts of data like physical data centers.

The MIT co-authors of the study include first author Ki Seok Kim, Seunghwan Seo, Doyoon Lee, Jung-El Ryu, Jekyung Kim, Jun Min Suh, June-chul Shin, Min-Kyu Song, Jin Feng and Sangho Lee, as well as collaborators from the Samsung Advanced Institute of Technology, Sungkyunkwan University in South Korea and the University of Texas at Dallas.

Tiny "germ pockets"

In 2023, Kim's group reported a method they had developed to grow high-quality semiconductor materials on amorphous surfaces, similar to the topography of semiconductor circuits on finished chips. The material they grew was a 2D material known as "transition-metal dichalcogenides" (TMD), which is considered a promising successor to silicon for the production of smaller, high-performance transistors.

TMDs combine extreme thinness with outstanding electronic and optical properties that are of interest both in basic research and in high-tech applications. They are considered promising materials to complement or even replace silicon in microelectronics, especially in areas such as flexible electronics and miniaturization. Such materials can retain their semiconducting properties even at a size of only one atom, while the performance of silicon decreases significantly.

In their earlier work, Kim's team grew TMDs on silicon wafers with amorphous coatings as well as on existing TMDs. To arrange the atoms in a monocrystalline form instead of a polycrystalline disorder, Kim and colleagues covered a silicon wafer with a very thin layer of silicon dioxide, which they provided with tiny openings or pockets—a mask. They then allowed a gas containing atoms to flow over the mask and found that the atoms settled in the pockets as "nuclei". The pockets confined the nuclei so that they grew in regular, single-crystal patterns. At that time, however, the method only worked at around +900 °C (1,652°F).

"You have to grow this monocrystalline material below +400 °C (752 °F) , otherwise the underlying circuit will be completely cooked and ruined," says Kim. "So our homework was to develop a similar technique at temperatures below +400 °C (752 °F). If we could do that, the impact would be significant."

Assembly technology

In their new work, the team attempted to refine the method to grow single-crystal 2D materials at sufficiently low temperatures. They found a surprisingly simple solution in metallurgy.

When metallurgists pour molten metal into a mold, nucleation begins. As the molten metal cools, the temperature drops below the melting point and the first atom clusters form solid nuclei. Metallurgists have found that this nucleation is most likely to occur at the edges of a mold into which molten metal is poured. "It is known that nucleation at the edges requires less energy—and heat," explains Kim. "We have adopted this concept from metallurgy."

The team attempted to grow single-crystal TMDs on a silicon wafer that already had transistor circuits on it. First, they covered the circuits with a mask of silicon dioxide, just as in their previous work. They then attached "TMD seeds" to the edges of each pocket of the mask and found that these edge seeds grew into single crystalline material at temperatures as low as +380°C (716 °F). Germs that grew further away from the edges of the mask required a higher temperature to form monocrystalline material.

The researchers went one step further and used the new method to produce a multilayer chip with alternating layers of two different TMDs. In this case, it was molybdenum disulphide, a promising material candidate for the production of n-type transistors, and tungsten diselenide, a material suitable for the production of p-type transistors. The team succeeded in growing both materials in single-crystal form directly on top of each other without the need for an intermediate silicon wafer. According to Kim, this method doubles the density of a chip's semiconductor elements, in particular the metal-oxide semiconductor (CMOS), which is a basic building block of modern logic circuits.

"A product realized with our technology is not only a 3D logic chip, but also 3D memory combined," says Kim. "With our growth-based monolithic 3D method, you could grow dozens to hundreds of logic and memory layers directly on top of each other, and they would be able to communicate optimally."

"Conventional 3D chips were fabricated with silicon wafers in between by drilling holes in the wafer - a process that limits the number of stacked layers, vertical alignment resolution and yield," adds first author Kiseok Kim. "Our growth-based method solves all these problems at once." To commercialize the stackable chip design, Kim has founded a company, FS2 (Future Semiconductor 2D Materials). "We've shown a concept for small device arrays so far," he said. "The next step is to scale up to show professional operation of AI chips." (sb)

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